• JSTS:Journal of Semiconductor Technology and Science
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• 제10권3호
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• pp.213-224
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• 2010

An optically controlled silicon MESFET (OPFET) was fabricated by diffusion process to enhance the quantum efficiency, which is the most important optoelectronic device performance usually affected by ion implantation process due to large number of process induced defects. The desired impurity distribution profile and the junction depth were obtained solely with diffusion, and etching processes monitored by atomic force microscope, spreading resistance profiling and C-V measurements. With this approach fabrication induced defects are reduced, leading to significantly improved performance. The fabricated OPFET devices showed proper I-V characteristics with desired pinch-off voltage and threshold voltage for normally-on devices. The peak photoresponsivity was obtained at 620 nm wavelength and the extracted external quantum efficiency from the photoresponse plot was found to be approximately 87.9%. This result is evidence of enhancement of device quantum efficiency fabricated by the diffusion process. It also supports the fact that the diffusion process is an extremely suitable process for fabrication of high performance optoelectronic devices. The maximum gain of OPFET at optical modulated signal was obtained at the frequency of 1 MHz with rise time and fall time approximately of 480 nS. The extracted transconductance shows the possible potential of device speed performance improvements for shorter gate length. The results support the use of a diffusion process for fabrication of high performance optoelectronic devices.

• 한국레이저가공학회지
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• 제14권4호
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• pp.14-20
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• 2011

The advantage of using lasers for through silicon via (TSV) drilling is that they allow higher flexibility during manufacturing because vacuums, lithography, and masks are not required; furthermore, the lasers can be applied to metal and dielectric layers other than silicon. However, conventional nanosecond lasers have disadvantages including that they can cause heat affection around the target area. In contrast, the use of a picosecond laser enables the precise generation of TSVs with a smaller heat affected zone. In this study, a comparison of the thermal and crystallographic defect around laser-drilled holes when using a picosecond laser beam with varing a fluence and repetition rate was conducted. Notably, the higher fluence and repetition rate picosecond laser process increased the experimentally recast layer, surface debris, and dislocation around the hole better than the high fluence and repetition rate. These findings suggest that even the picosecond laser has a heat accumulation effect under high fluence and short pulse interval conditions. To eliminate these defects under the high speed process, the CDE (chemical downstream etching) process was employed and it can prove the possibility to applicate to the TSV industry.

• 반도체디스플레이기술학회지
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• 제12권2호
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• pp.79-84
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• 2013

Nanoimprint lithography (NIL) is the next generation photolithography process in which the photoresist is dispensed onto the substrate in its liquid form and then imprinted and cured into a desired pattern instead of using traditional optical system. There have been considerable attentions on NIL due to its potential abilities that enable cost-effective and high-throughput nanofabrication to the display device and semiconductor industry. Although one of the current major research trends of NIL is large-area patterning, the technical difficulties to keep the uniformity of the residual layer become severer as the imprinting area increases more and more. In this paper, with the rolling type imprinting process, a mold, placed upon the $2^{nd}$ generation TFT-LCD glass sized substrate($370{\times}470mm^2$), is rolled by a rubber roller to achieve a uniform residual layer. The prediction of residual layer thickness of the photoresist by rolling of the rubber roller is crucial to design the rolling type imprinting process, determine the rubber roller operation conditions-mpressing force & feeding speed, operate smoothly the following etching process, and so forth. First, using the elasticity theory of contact problem and the empirical equation of rubber hardness, the contact length between rubber roller and mold is calculated with consideration of the shape and hardness of rubber roller and the pressing force to rubber roller. Next, using the squeeze flow theory to photoresist flow, the residual layer thickness of the photoresist is calculated with information of the viscosity and initial layer thickness of photoresist, the shape of mold pattern, feeding speed of rubber roller, and the contact length between rubber roller and mold previously calculated. Last, the effects of rubber roller operation conditions, impressing force & feeding speed, on the residual layer thickness are analyzed with consideration of the shape and hardness of rubber roller.

• 전자공학회논문지A
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• 제29A권4호
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• pp.38-48
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• 1992

OEIC(Optoelectronic Integrated Circuit)'s can be integrated horizontally or vertically. Horizontal integration approach is, however, more immune to parasitic and more universally applicable. In this paper, a structural modeling, fabrication and characterization of PIN photodiodes which can be used in the horizontal integration are performed. For device modeling, we build a transmission line model from 2-D device simulation, from which lumped model parameters are extracted. The speed limits of the PIN photodiodes can also be calculated under various structural conditions from the model. Thus optimum design of horizontally integrated PIN photodiodes for high speed operation are possible. Such InGaAs/InP PIN photodiodes for long-wavelength communications are fabricated using pit etch, epi growth, planarization, diffusion and metallization processes. Planarization process using both RIE and wet etching and diffusion process using evaporated Zn$_{3}P_{2}$ film are developed. Characterization of the fabricated devices is performed through C-V and I-V measurements. At a reserve bias of 10V, the dark current is less than 5nA and capacitance is about 0.4pF. The calculated bandwidth using the measured series resistance and capacitance is about 4.23GHz.

• 한국재료학회지
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• 제14권6호
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• pp.413-419
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• 2004

Recently, Silicon On Insulator (SOI) devices emerged to achieve better device characteristics such as higher operation speed, lower power consumption and latch-up immunity. Nevertheless, there are many detrimental defects in SOI wafers such as hydrofluoric-acid (HF)-defects, pinhole, islands, threading dislocations (TD), pyramid stacking faults (PSF), and surface roughness originating from quality of buried oxide film layer. Although the number of defects in SOI wafers has been greatly reduced over the past decade, the turn over of high-speed microprocessors using SOI wafers has been delayed because of unknown defects in SOI wafers. A new characterization method is proposed to investigate the crystalline quality, the buried oxide integrity and some electrical parameters of bonded SOI wafers. In this study, major surface defects in bonded SOI are reviewed using HF dipping, Secco etching, Cu-decoration followed by focused ion beam (FIB) and transmission electron microscope (TEM).

• 한국분무공학회지
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• 제16권1호
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• pp.27-36
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• 2011

The impact force on the single and overlap region of twin spray was experimentally evaluated using visualization method in full cone type swirl nozzle spray. Visualization of spray was conducted to obtain the spray angle and breakup process. The photography/imaging technique, based on Particle Image Velocimetry (PIV) using high-speed camera, was adopted for the direct observation of droplet motion and axial velocity measurement, respectively. Droplet size was measured by Particle Motion Analyze System (PMAS). The purpose of this study is to provide fundamental information of spray characteristics, such as impact force, for higher etching factor in the practical wet etching system. It was found that the spray angle, axial velocity and impact force were increased with increasing the nozzle pressure while droplet size decreased with increasing the nozzle pressure. Droplet size increased as the distance from nozzle tip was decreased. The impact force of twin spray in the overlap region was about 63.29, 67.02, 52.41% higher than that of single spray at 40, 50 and 60 mm of nozzle pitch, respectively. Also, the nozzle pitch was one of the important factors in the twin spray characteristics.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.523-523
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• 2012

As the wafer geometric requirements continuously complicated and minutes in tens of nanometers, the expectation of real-time add-on sensors for in-situ plasma process monitoring is rapidly increasing. Various industry applications, utilizing plasma impedance monitor (PIM) and optical emission spectroscopy (OES), on etch end point detection, etch chemistry investigation, health monitoring, fault detection and classification, and advanced process control are good examples. However, process monitoring in semiconductor manufacturing industry requires non-invasiveness. The hypothesis behind the optical monitoring of plasma induced ion current is for the monitoring of plasma induced charging damage in non-invasive optical way. In plasma dielectric via etching, the bombardment of reactive ions on exposed conductor patterns may induce electrical current. Induced electrical charge can further flow down to device level, and accumulated charges in the consecutive plasma processes during back-end metallization can create plasma induced charging damage to shift the threshold voltage of device. As a preliminary research for the hypothesis, we performed two phases experiment to measure the plasma induced current in etch environmental condition. We fabricated electrical test circuits to convert induced current to flickering frequency of LED output, and the flickering frequency was measured by high speed optical plasma monitoring system (OPMS) in 10 kHz. Current-frequency calibration was done in offline by applying stepwise current increase while LED flickering was measured. Once the performance of the test circuits was evaluated, a metal pad for collecting ion bombardment during plasma etch condition was placed inside etch chamber, and the LED output frequency was measured in real-time. It was successful to acquire high speed optical emission data acquisition in 10 kHz. Offline measurement with the test circuitry was satisfactory, and we are continuously investigating the potential of real-time in-situ plasma induce current measurement via OPMS.

• 마이크로전자및패키징학회지
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• 제18권4호
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• pp.49-53
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• 2011

TSV(through-silicon-via)를 이용한 3차원 Si 칩 패키징 공정 중 전기 도금을 이용한 비아 홀 내 Cu 고속 충전과 범핑 공정 단순화에 관하여 연구하였다. DRIE(deep reactive ion etching)법을 이용하여 TSV를 제조하였으며, 비아홀 내벽에 $SiO_2$, Ti 및 Au 기능 박막층을 형성하였다. 전도성 금속 충전에서는 비아 홀 내 Cu 충전율을 향상시키기 위하여 PPR(periodic-pulse-reverse) 전류 파형을 인가하였으며, 범프 형성 공정에서는 리소그라피(lithography) 공정을 사용하지 않는 non-PR 범핑법으로 Sn-3.5Ag 범프를 형성하였다. 전기 도금 후, 충전된 비아의 단면 및 범프의 외형을 FESEM(field emission scanning electron microscopy)으로 관찰하였다. 그 결과, Cu 충전에서는 -9.66 $mA/cm^2$의 전류밀도에서 60분간의 도금으로 비아 입구의 도금층 과성장에 의한 결함이 발생하였고, -7.71 $mA/cm^2$에서는 비아의 중간 부분에서의 도금층 과성장에 의한 결함이 발생하였다. 또한 결함이 생성된 Cu 충전물 위에 전기 도금을 이용하여 범프를 형성한 결과, 범프의 모양이 불규칙하고, 균일도가 감소함을 나타내었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.206-209
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• 2002

With the progress of semiconductor processing technology, avalanohe photodiodes (APDs) based on InP/InGaAs are used for high-speed optical receiver modules. Planar-type APDs give higher reliability than mesa-type APDs. However, Planar-type APDs are struggled with a problem of intensed electric field at the junction curvature, which causes edge breakdown phenomena at the junction periphery. In this paper, we focused on studying the effects of junction curvature for APDs performances by different etching processes followed by single diffusion to from p-n junction. The performance of each process is characterized by observing electric field profiles and carrier generation rates. From the results, it can be understood to predict the optimum structure, which can minimize edge breakdown and improve the manufacturability.

• 대한금속재료학회지
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• 제49권5호
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.