• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.463-466
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• 2000

According to the development of the semiconductor micro device technology, IC chip trends the high integrated, low power tendency. Nowadays, it can be showed the tendency of single chip in system level. But in the system level, IC operates by multi power supply voltages. So, semiconductor process is necessary for these multi power operation. Therefore, in this paper, dual gate high voltage device that operate by multi power supply of 5V and 20V fabricated in the 0.5${\mu}{\textrm}{m}$ CMOS process technology and its electrical characteristics were analyzed. The result showed that the characteristics of the 5V device almost met with the SPICE simulation, the SPICE parameters are the same as the single 5V device process. And the characteristics of 20V device showed that gate length 3um device was available without degradation. Its current was 520uA/um, 350uA/um for NMOS, PMOS and the breakdown voltages were 25V, 28V.

• ETRI Journal
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• v.16 no.4
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• pp.1-11
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• 1995

A GaAs power metal semiconductor field effect transistor (MESFET) operating at a voltage as low as 3.3V has been developed with the best performance for digital handheld phone. The device has been fabricated on an epitaxial layer with a low-high doped structure grown by molecular beam epitaxy. The MESFET, fabricated using $0.8{\mu}m$ design rule, showed a maximum drain current density of 330 mA/mm at $V_{gs}$ =0.5V and a gate-to-drain breakdown volt-age of 28 V. The MESFET tested at a 3.3 V drain bias and a 900 MHz operation frequency displayed an output power of 32.5-dBm and a power added efficiency of 68%. The associate power gain at 20 dBm input power and the linear gain were 12.5dB and 16.5dB, respectively. Two tone testing measured at 900.00MHz and 900.03MHz showed that a third-order intercept point is 49.5 dBm. The power MESFET developed in this work is expected to be useful as a power amplifying device for digital hand-held phone because the high linear gain can deliver a high power added efficiency in the linear operation region of output power and the high third-order intercept point can reduce the third-order intermodulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.377-387
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• 2012

An intrinsic small signal equivalent circuit model of Cylindrical/Surrounded gate MOSFET is proposed. Admittance parameters of the device are extracted from circuit analysis and intrinsic circuit elements are presented in terms of real and imaginary parts of the admittance parameters. S parameters are then evaluated and justified with the simulated data extracted from 3D device simulation.

• Journal of Power Electronics
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• v.9 no.1
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• pp.36-42
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• 2009

This paper presents a review of an improved high power-high frequency III-V wide bandgap (WBG) semiconductor device, Gallium Nitride (GaN). The device offers better efficiency and thermal management with higher switching frequency. By having higher blocking voltage, GaN can be used for high voltage applications. In addition, the weight and size of passive components on the printed circuit board can be reduced substantially when operating at high frequency. With proper management of thermal and gate drive design, the GaN power converter is expected to generate higher power density with lower stress compared to its counterparts, Silicon (Si) devices. The main contribution of this work is to provide additional information to young researchers in exploring new approaches based on the device's capability and characteristics in applications using the GaN power converter design.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.5
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• pp.290-294
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• 2003

Using a backpropagation neural network (BPNN), a high power semiconductor device was empirically modeled. The device modeled is a n-LDMOSFET and its electrical characteristics were measured with a HP4156A and a Tektronix curve tracer 370A. The drain-source current $(I_{DS})$ was measured over the drain-source voltage $(V_{DS})$ ranging between 1 V to 200 V at each gate-source voltage $(V_{GS}).$ For each $V_{GS},$ the BPNN was trained with 100 training data, and the trained model was tested with another 100 test data not pertaining to the training data. The prediction accuracy of each $V_{GS}$ model was optimized as a function of training factors, including training tolerance, number of hidden neurons, initial weight distribution, and two gradients of activation functions. Predictions from optimized models were highly consistent with actual measurements.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.159-160
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• 2015

Recently, it is increased to use the portable device with small size. It is also increasing for demand of a small size adapter. To reduce the size of components, switching frequency has to be increased. But it causes higher switching loss and temperature of components. Especially, the temperature of adapter must be limited because adapter can be easily touched when portable device is being charged. To reduce temperature of adapter, high efficiency is essential. To solve this problem, this paper proposes design of resonance frequency optimization for LLC converter with high efficiency and low temperature of passive components.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.386-387
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• 2013

This paper provides a comparison of high power semiconductor devices in 5MW-class Permanent Magnet Synchronous Generator (PMSG) Medium Voltage (MV) wind turbines. High power semiconductor devices of IGBT module type, IGBT press-pack type, and IGCT of both 4.5kV and 6.5kV are considered in this paper. Benchmarking is performed based on neutral-point clamed 3-level back-to-back type voltage source converter supplied from grid voltage of 4160V. The feasible number of semiconductor devices in parallel is designed through the loss analysis considering both conduction and switching losses under the given operating conditions of 5MW-class PMSG wind turbines, particularly for the application in offshore wind farms. The loss analysis is confirmed through PLECS simulations. The comparison result shows that IGBT press-pack type semiconductor device has the highest efficiency and IGCT has the lowest cost factor considering the necessary auxiliary components.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.365-368
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• 2004

Charge compensation effects in multi-resurf structure make possible to obtain high breakdown volatage and low on-resistance in vertical MOSFET. In this paper, electrical characteristics of the vertical MOSFET with multi epitaxial layer is presented. Proposed device has n and p-pillar for obtaining the charge compensation effects and The doping concentration each pillar is varied from $5{\times}10^{14}\;to\;1{\times}10^{16}/cm^3$. The thickness of the proposed device also varied from $400{\mu}m\;to\;500{\mu}m$. Due to the charge compensation effects, 4500V of breakdown voltage can be obtained.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.370-376
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• 2012

In this work, design considerations for high-performance silicon photodetector are thoroughly investi- gated. Besides the critical dimensions of device, guidelines for process architecture are suggested. Abiding by those criteria for improving both direct-current (DC) and alternating-current (AC) perfor- mances, a high-speed low-operation power silicon photodetector based on p-i-n structure for optical interconnect has been designed by device simulation. An $f_{-3dB}$ of 80 GHz at an operating voltage of 1 V was obtained.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.353-356
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• 2004

This paper discribes the analysis of the I-V characteristics of 4H-SiC DiMOSFET with single epi-layer Silicon Carbide has been around for over a century. However, only in the past two to three decades has its semiconducting properties been sufficently studied and applied, especially for high-power and high frequency devices. We present a numerical simulation-based optimization of DiMOSFET using the general-purpose device simulator MINIMIS-NT. For simulation, a loin thick drift layer with doping concentration of $5{\times}10^{15}/cm^3$ was chosen for 1000V blocking voltage design. The simulation results were used to calculate Baliga's figure of Merit (BFOM) as the criterion structure optimization and comparison.