• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.281-284
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• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권2호
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• pp.73-79
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• 2011

This paper describes a reset-free delay-locked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop's lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-${\mu}m$ CMOS process, post-layout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 MHz. It occupies 0.04 $mm^2$ and dissipates 16.6 mW at 1.2 GHz.

• 전기전자학회논문지
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• 제22권4호
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• pp.1158-1162
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• 2018

안티-하모닉락 기능을 가지는 고속-락킹 MDLL 기반의 디지털 클락 주파수 증배기를 소개한다. 제안하는 디지털 주파수 증배기는 하모닉락 문제 없이 빠른 락킹 시간을 구현하기 위하여 새로운 MSB-구간 검색 알고리즘을 사용한다. 제안하는 디지털 MDLL 주파수 증배기는 65nm CMOS 공정으로 설계되었으며, 1 GHz ~ 3 GHz의 출력 동작주파수 영역을 가진다. 제안하는 디지털 MDLL은 프로그래머블한 N/M (N=1, 4, 5, 8, 10, M=1, 2, 3)의 분수배 주파수 증배 기능을 제공한다. 제안하는 MDLL은 1GHz에서 3.52 mW의 전력을 소모하고, 14.07 ps의 피크-투-피크 (p-p) 지터를 갖는다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 추계학술대회
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• pp.95-97
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• 2018

The power quality of Single Phase Grid-Connected Inverters (GCIs) has received much attention with the increasing number of Distributed Generation (DG) systems. However, the performance of single phase GCIs get degraded due to several factors such as the grid voltage harmonics, the dead time effect, and the turn ON/OFF of the switches, which causes the harmonics at the output of GCIs. Therefore, it is not easy to satisfy the harmonic standards such as IEEE 519 and P1547 without the help of harmonic compensator. To meet the harmonic standards a certain kind of harmonic controller needs to be added to the current control loop to effectively mitigate the low order harmonics. In this paper, the harmonic compensation is performed using a novel robust harmonic compensation method based on Digital Lock-in Amplifier (DLA). In the proposed technique, DLAs are used to extract the amplitude and phase information of the harmonics from the output current and compensate it by using a simple PI controller in the feedforward manner. In order to show the superior performance of the proposed harmonic compensation technique, it is compared with those of conventional harmonic compensation methods in terms of the effectiveness of harmonic elimination, complexity, and implementation. The validity of the proposed harmonic compensation techniques for the single phase GCIs is verified through the experimental results with a 5kW single phase GCI. Index Terms -Single Phase Grid Connected Inverter (SPGCI), Harmonic Compensation Method, Total Harmonic Distortion (THD) and Harmonic Standard.

• 전기전자학회논문지
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• 제21권4호
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• pp.416-419
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• 2017

본 논문에서는 고속 DDR3/DDR4 SDRAM을 위한 새로운 디지털 지연고정루프 (delay-locked loop: DLL)를 제안한다. 제안하는 디지털 DLL은 디지털 지연라인의 boundary switching 문제에 의한 jitter 증가 문제를 제거하기 위하여 위상보간 (phase interpolation) 방식의 파인지연라인 (fine delay line)을 채택하였다. 또한, 제안하는 디지털 DLL은 harmonic lock 문제를 제거하기 위하여 새로운 점진직 검색 (gradual search) 알고리즘을 사용한다. 제안하는 디지털 DLL은 1.1V, 38-nm CMOS DRAM 공정으로 설계되었으며, 0.25-2.0 GHz의 주파수 동작 영역을 가진다. 2.0 GHz에서 1.1 ps의 피크-투-피크 (p-p) 지터를 가지며, 약 13 mW의 전력소모를 가진다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 추계학술대회
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• pp.259-262
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• 2012

본 논문에서는 125 MHz 동작 주파수에서 64개 위상의 클럭을 출력하는 지연 고정 루프 (DLL: delay-locked loop)을 제안한다. 제안된 다중 지연 고정 루프는 delay line의 선형성을 개선하기 위해 $4{\times}8$ matrix 구조의 delay line을 사용한다. CMOS multiplexer와 inverter-based interpolator를 이용하여 $4{\times}8$ matrix 기반의 delay line에서 출력된 32개 위상의 클럭으로부터 64개 위상의 클럭을 생성한다. 또한 DLL에서 harmonic lock을 방지하기 위해 클럭의 duty cycle ratio에 무관한 initial phase locking을 위한 회로가 제안된다. 제안된 지연 고정 루프는 1.8 V의 공급전압을 이용하는 $0.18-{\mu}m$ CMOS 공정에서 설계된다. 시뮬레이션된 DLL은 40 MHz에서 200 MHz의 동작 주파수 범위를 가진다. 125 MHz 동작 주파수에서 최악의 위상 오차와 jitter는 각각 +11/-12 ps와 6.58 ps이다.

• 전력전자학회논문지
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• 제25권5호
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• pp.358-368
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• 2020

Grid-connected inverters (GCIs) based on renewable energy sources play an important role in enhancing the sustainability of a society. Harmonic standards, such as IEEE 519 and P1547, which require the total harmonic distortion (THD) of the output current to be less than 5%, should be satisfied when GCIs are connected to a grid. However, achieving a current THD of less than 5% is difficult for GCIs with an output filter under a distorted grid condition. In this study, a novel harmonic compensation method that uses a digital lock-in amplifier (DLA) is proposed to eliminate harmonics effectively at the output of GCIs. Accurate information regarding harmonics can be obtained due to the outstanding performance of DLA, and such information is used to eliminate harmonics with a simple proportional-integral controller in a feedforward manner. The validity of the proposed method is verified through experiments with a 5 kW single-phase GCI connected to a real grid.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2019년도 전력전자학술대회
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• pp.77-79
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• 2019

Islanding detection is one of the most important issues for the distributed generation (DG) systems connected to the power grid. The conventional passive islanding detection methods inherently have a non-detection zone (NDZ), and active islanding detection methods may deteriorate the power quality of a power system. This paper proposes a novel hybrid islanding detection method based on Digital Lock-In Amplifier with no NDZ by monitoring the harmonics present in the grid. Proposed method detects islanding by passively monitoring the grid voltage harmonics and verify it by injecting small perturbation for only three-line cycles. Unlike FFT for the harmonic extraction, DLA HC have lower computational burden, moreover, DLA can monitor harmonic in real time, whereas, FFT has certain propagation delay. The simulation results are presented to highlight the effectiveness of the proposed technique. In order to prove the performance of the proposed method it is compared with several passive islanding detection methods. The experimental results confirm that the proposed method exhibits outstanding performance as compared to the conventional methods.

• Ocean and Polar Research
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• 제33권3호
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• pp.309-319
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• 2011

This is a preliminary study of the feasibility of obtaining reliable tidal current harmonic constants, using one month of current observations, to verify the accuracy of a tidal model. An inference method is commonly used to separate out the tidal harmonic constituents when the available data spans less than a synodic period. In contrast to tidal constituents, studies of the separation of tidal-current harmonics are rare, basically due to a dearth of the long-term observation data needed for such experiments. We conducted concurrent and monthly harmonic analyses for tidal current velocities and heights, using 2 years (2006 and 2007) of current and sea-level records obtained from the Tidal Current Signal Station located in the narrow waterway in front of Incheon Lock, Korea. Firstly, the l-year harmonic analyses showed that, with the exception of $M_2$ and $S_2$ semidiurnal constituents, the major constituents were different for the tidal currents and heights. $K_1$, for instance, was found to be the 4th major tidal constituent but not an important tidal current constituent. Secondly, we examined monthly variation in the amplitudes and phase-lags of the $S_2$ and $K_1$ current-velocity and tide constituents over a 23-month period. The resultant patterns of variation in the amplitudes and phase-lags of the $S_2$ tidal currents and tides were similar, exhibiting a sine curve form with a 6-month period. Similarly, variation in the $K_1$ tidal constant and tidal current-velocity phase lags showed a sine curve pattern with a 6-month period. However, that of the $K_1$ tidal current-velocity amplitude showed a somewhat irregular sine curve pattern. Lastly, we investigated and tested the inference methods available for separating the $K_2$ and $S_2$ current-velocity constituents via monthly harmonic analysis. We compared the effects of reduction in monthly variability in tidal harmonic constants of the $S_2$ current-velocity constituent using three different inference methods and that of Schureman (1976). Specifically, to separate out the two constituents ($S_2$ and $K_2$), we used three different inference parameter (i.e. amplitude ratio and phase-lag diggerence) values derived from the 1-year harmonic analyses of current-velocities and tidal heights at (near) the short-term observation station and from tidal potential (TP), together with Schureman's (1976) inference (SI). Results from these four different methods reveal that TP and SI are satisfactorily applicable where results of long-term harmonic analysis are not available. We also discussed how to further reduce the monthly variability in $S_2$ tidal current-velocity constants.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제51권1호
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• pp.23-33
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• 2002

A hysteresis control is widely used to control output current of inverter. A hysteresis bandwidth is affected by system parameters such as source voltage, device on/off time, load inductance and resistance. The frequency limiter is used to protect switching devices overload. In the conventional hysteresis controller, a lock-out circuit with D-latch and timer is used to device protection circuit. But switching delay time and harmonic components are appeared in output current. In this paper the performance of lock-out circuit is tested, and new circuit for switching device fault protection is proposed ad it's performance is simulated.