• 한국정보통신학회논문지
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• 제21권4호
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• pp.774-780
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• 2017

본 논문은 HEVC의 엔트로피 코딩방법인 CABAC 부호화기를 위한 효율적인 이진 산술 부호화기 하드웨어 구조를 제안한다. CABAC은 HEVC 표준에서 사용되는 엔트로피 코딩 방법으로 통계적 중복성을 제거하여 영상의 높은 압축률을 지원한다. 하지만 이진 산술 부호화(Binary Arithmetic Encode)는 데이터 간의 의존 관계가 높아 병렬처리가 어렵고 실시간 처리의 지연이 발생 된다. 제안하는 이진 산술 부호화기는 입력으로 들어오는 빈을 고속으로 처리하기 위하여 재정규화 과정을 분리 시켜 동작하도록 설계한다. 기존의 반복적인 알고리즘을 병렬적으로 처리함으로써 최대지연시간(Critical Path)을 최적으로 줄일 수 있는 4단계의 파이프라인 구조로 설계하였다. 또한, 멀티-빈 구조를 적용하여 클록 사이클 당 3개의 빈을 처리한다. 제안하는 CABAC의 이진 산술 부호화기는 Verilog-HDL로 설계하였으며 65nm 공정으로 합성하였다. 합성 결과 게이트수는 8.07K 이며 최대 동작주파수는 769MHz로 최대 빈 처리량은 2307Mbin/s이다. 제안하는 하드웨어 구조는 기존의 이진 산술 부호화기와 비교하여 최대 빈 처리량이 26% 만큼 증가 하였다.

• 대한전자공학회논문지SD
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• 제43권3호
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• pp.33-39
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• 2006

Divide-and-Conquer방법은 병렬 곱셈기의 구성에 잘 적용되며 가장 대표적으로 카라슈바 방법이 있다. Leone은 최적 반복 회수를 카라슈바 알고리즘에 적용하였으며 Ernst는 다중 분할 카라슈바 방법을 제안하였다. 본 논문에서는 카라슈바 알고리즘에서 불필요한 연산이 제거된 불필요한 연산이 없는 카라슈바 알고리즘과 효율적인 하드웨어 구조를 제안한다. 본 논문에서 제안하는 알고리즘은 기존의 카라슈바 알고리즘에 비교하여 같은 시간 복잡도를 가지나 공간 복잡도를 효율적으로 감소시킨다. 특히 확장체의 차수 n이 홀수 및 소수일 때 더 효율적이며 최대 43%까지 공간 복잡도를 줄일 수 있다.

• 전자공학회논문지C
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• 제34C권9호
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• pp.22-32
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• 1997

This paper proposes an imprecise compuitation model for DCT considering QOS of images and a two dimensional DCT architecture for imprecise computations. In case that many processes are scheduling in a hard real time system, the system resources are shared among them. Thus all processes can not be allocated enough system resources (such as processing power and communication bandwidth). The imprecise computtion model can be used to provide scheduling flexibility and various QOS(quality of service)levels, to enhance fault tolerance, and to ensure service continuity in rela time systems. The DCT(discrete cosine transform) is known as one of popular image data compression techniques and adopted in JPEG and MPEG algorithms since the DCT can remove the spatial redundancy of 2-D image data efficiently. Even though many commercial data compression VLSI chips include the DCST hardware, the DCT computation is still a very time-consuming process and a lot of hardware resources are required for the DCT implementation. In this paper the DCT procedure is re-analyzed to fit to imprecise computation model. The test image is simulated on teh base of this model, and the computation time and the quality of restored image are studied. The row-column algorithm is used ot fit the proposed imprecise computation DCT which supports pipeline operatiions by pixel unit, various QOS levels and low speed stroage devices. The architecture has reduced I/O bandwidth which could make its implementation feasible in VLSI. The architecture is proved using a VHDL simulator in architecture level.

• Nuclear Engineering and Technology
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• 제55권4호
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• pp.1528-1539
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• 2023

Since the leakage of sodium in an SFR (sodium-cooled fast reactor) causes an explosion upon reaction with air and water, sodium leakages represent an important safety issue. In this study, a novel technique for improving the reliability of sodium leakage detection applying DDVR (dynamic data validation and reconciliation) is proposed and verified to resolve this technical issue. DDVR is an approach that aims to improve the accuracy of a target system in a dynamic state by minimizing random errors, such as from the uncertainty of instruments and the surrounding environment, and by eliminating gross errors, such as instrument failure, miscalibration, or aging, using the spatial redundancy of measurements in a physical model and the reliability information of the instruments. DDVR also makes it possible to estimate the state of unmeasured points. To validate this approach for supporting sodium leakage detection, this study applies experimental data from a sodium leakage detection experiment performed by the Korea Atomic Energy Research Institute. The validation results show that the reliability of sodium leakage detection is improved by cooperation between DDVR and hardware measurements. Based on these findings, technology integrating software and hardware approaches is suggested to improve the reliability of sodium leakage detection by presenting the expected true state of the system.

• 한국정보통신학회논문지
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• 제21권3호
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• pp.594-600
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• 2017

본 논문에서는 고성능 HEVC(High Efficiency Video Coding) 부호기를 위한 전역탐색 기반의 움직임추정 알고리즘과 이에 적합한 하드웨어 구조를 제안한다. HEVC 화면 간 예측에서의 움직임추정은 시간적 중복성을 제거하기 위하여 보간 된 참조 픽쳐에서 현재 PU와 상관도가 높은 예측 블록을 탐색하는 과정으로 전역탐색 알고리즘과 고속탐색 알고리즘을 이용한다. 전역 탐색 기법은 주어진 탐색 영역내의 모든 후보 블록에 대하여 움직임을 예측하기 때문에 최적의 결과를 보장하지만 연산량 및 연산시간이 많은 단점을 지닌다. 그러므로 본 논문에서는 Inter Prediction의 연산량 및 연산시간을 줄이기 위해 전역탐색에서 SAD연산을 재사용하여 연산복잡도를 줄이는 새로운 알고리즘을 제안하고 이에 적합한 하드웨어 구조를 제안한다. 제안된 알고리즘은 HEVC 표준 소프트웨어 HM16.12에 적용하여 검증한 결과 기존 전역탐색 알고리즘보다 연산시간은 61%, BDBitrate는 11.81% 감소하였고, BDPSNR은 약 0.5% 증가하였다. 또한 하드웨어설계 결과 최대 동작주파수는 255 Mhz, 총 게이트 수는 65.1K 이다.

• IEIE Transactions on Smart Processing and Computing
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• 제5권1호
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• pp.29-34
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• 2016

A controller area network (CAN) controller is an integral part of an electronic control unit, particularly in an advanced driver assistance system application, and its characteristics should always be advantageous in all aspects of functionality especially in real time application. The cost should be low, while maintaining the functionality and reliability of the technology. However, a CAN protocol implementing serial operation results in slow throughput, especially in a cyclical redundancy checking (CRC) unit. In this paper, digital signal processing (DSP) algorithms are implemented, namely pipelining, unfolding, and retiming the CAN controller in the CRC unit, particularly for the encoder and decoder sections. It must attain a feasible iteration bound, a critical path that is appropriate for a CAN system, and must obtain a superior design of a high-speed parallel circuit for the CRC unit in order to have a faster transmission rate. The source code for the encoder and decoder was formulated in the Verilog hardware description language.

• Journal of Advanced Marine Engineering and Technology
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• 제25권2호
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• pp.375-382
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• 2001

In this study, an adapted Turbo Coding Algorithm for reducing communication error of a fire detection system for marine vessels, especially image transmission via power lone. Because it is necessary that this system communicate larger and faster than previous method, this study carried out enhancement a decoding speed by adaptation CRC with Turbo Code Algorithm, improvement of metric method, and reduction of decoding delay by using of Center-to-Top method. And the results are as follows: (1) Confirmed that a Turbo Code is so useful methods for reducing communication error in lots of noise environments. (2)Proposed technology in this study speed increasing method of Turbo Coding Algorithm proves 2 times faster than normal Turbo Code and communication error reducing as well in the board made by VHDL software & chips ALTERA company.

• 전기학회논문지
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• 제62권9호
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• pp.1249-1254
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• 2013

A torque control algorithm suitable for detecting an open circuit failure in which one of the three phases is unable to supply power to a motor in the permanent magnet synchronous motor is presented in this paper. When the failure occurs in the inverter, the output torque of motor is restricted. A new method which is implemented by using only a processor algorithm internally without any hardware redundancy circuit is proposed. A simulation and experimental study is carried out with a three phase inverter system to show the validity of the proposed method.

• Journal of Astronomy and Space Sciences
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• 제15권2호
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• pp.499-508
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• 1998

다목적 실용위성 관계시스템의 SOS(Satelite Operations Subsystem) 서브시스템은 위성에서 보내온 원격측정 데이터를 처리하여 위성의 상태를 감시하고 위성으로 원격명령을 전송하는 업무를 수행한다. 본 논문에서는 SOS 서브시스템의 신뢰성 및 가용성을 향상시키기 위하여 하드웨어와 소프트웨어를 이중화하여 데이터 손실을 최소화하도록 설계한 SOS의 동족 고장관리(dynamic fault management) 기법에 대하여 기술하였다. 또한 구현의 정당성을 확인하기 위한 성능 시험 방법을 제시하였으며 그에 대한 결과를 분석하였다.

• Journal of Power Electronics
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• 제14권6호
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• pp.1272-1280
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• 2014

This paper presents solutions for fault detection and diagnosis of two-level, three phase voltage-source inverter (VSI) topologies with IGBT devices. The proposed solutions combine redundant standby VSI structures and contactors (or relays) to improve the fault-tolerant capabilities of power electronics in applications with safety requirements. The suitable combination of these elements gives the inverter the ability to maintain energy processing in the occurrence of several failure modes, including short-circuit in IGBT devices, thus extending its reliability and availability. A survey of previously developed fault-tolerant VSI structures and several aspects of failure modes, detection and isolation mechanisms within VSI is first discussed. Hardware solutions for the protection of power semiconductors with fault detection and diagnosis mechanisms are then proposed to provide conditions to isolate and replace damaged power devices (or branches) in real time. Experimental results from a prototype are included to validate the proposed solutions.