• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.85-97
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• 2002

STUMPS has been widely used for built-in self-test of scan design with multiple scan chains. In the STUMPS architecture, there is very high correlation between the bit sequences in the adjacent scan chains. This correlation causes circuits lower the fault coverage. In order to solve this problem, an extra combinational circuit block(phase shifter) is placed between the LFSR and the inputs of STUMPS architecture despite the hardware overhead increase. This paper introduces an efficient test pattern generation technique and built-in self-test architecture for sequential circuits with multiple scan chains. The proposed test pattern generator is not used the input of LFSR and phase shifter, hence hardware overhead can be reduced and sufficiently high fault coverage is obtained. Only several XOR gates in each scan chain are required to modify the circuit for the scan BIST, so that the design is very simple.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.6
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• pp.322-329
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• 2000

BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.127-138
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• 2007

In this paper, we propose a new X-masking scheme for utilizing logic built-in self-test The new scheme exploits the phase-shifting network which is based on the shift-and-add property of maximum length pseudorandom binary sequences(m-sequences). The phase-shifting network generates mask-patterns to multiple scan chains by appropriately shifting the m-sequence of an LFSR. The number of shifts required to generate each scan chain mask pattern can be dynamically reconfigured during a test session. An iterative simulation procedure to synthesize the phase-shifting network is proposed. Because the number of candidates for phase-shifting that can generate a scan chain mask pattern are very large, the proposed X-masking scheme reduce the hardware overhead efficiently. Experimental results demonstrate that the proposed X-masking technique requires less storage and hardware overhead with the conventional methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.3 s.333
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• pp.35-42
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• 2005

This paper proposes a new reseeding methodology using a variable-rank multiple-polynomial linear feedback shift register (MP-LFSR). In the proposed reseeding scheme, a test cube with large number of specified bits is encoded with a high-rank polynomial, while a test cube with a small number of specified bits is encoded with a low-rank polynomial. Therefore, according to the number of specified bits in each test cube, the size of the encoded data can be optimally reduced. A variable-rank MP-LFSR can be implemented with a slight modification of a conventional MP-LFSR and Multiple Polynomial can be represented by adding just 1 bit to encoding data. The experimental results on the largest ISCAS'89 benchmark circuits show that the proposed methodology can provide much better encoding efficiency than the previous methods with adequate hardware overhead.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.526-531
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• 2003

Recently, many BIST(Built-in Self Test) schemes have been researched to reduce test time and hardware. But, most BIST schemes about pattern generation are for deterministic pattern generation. In this paper a new pseudo-random BIST scheme is provided to reduce the existing test hardware and keep a reasonable length of test time. Theoretical study demonstrates the possibility of the reduction of the hardware for pseudo-random test with some explanations and examples. Also the experimental results show that in the proposed test scheme the hardware for the pseudo-random test is much less than in the previous scheme and provide comparison of test time between the proposed scheme and the current one.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.29-35
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• 2010

In this paper we propose a new pattern generator for a BIST architecture that can reduce the power consumption during test application. The principle of the proposed method is to reconstruct an LFSR circuit to reduce WSAs of the heavy nodes by suppressing the heavy inputs. We propose algorithms for finding heavy nodes and heavy inputs. Using the Modified LFSR which consists of some AND/OR gates trees and an original LFSR, BIST applies modified test patterns to the circuit under test. The proposed BIST architecture with small hardware overhead effectively reduces the average power consumption during test application while achieving high fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 30.5%.

• The Transactions of the Korea Information Processing Society
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• v.5 no.9
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• pp.2378-2387
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• 1998

This thesis proposes a design algorithm of an efficient space response compactor for Built-In Self-Testing of VLSI circuits. The proposed design algorithm of space compactors can be applied independently from the structure of Circuit Cnder Test. There are high hardware overhead cost in conventional space response compactors and the fault coverage is reduced by aliasing which maps faulty circuit's response to fault-free one. However, the proposed method designs space response compactors with reduced hardware overheads and does not reduce the fault coverage comparing to conventional method. Also, the proposed method can be extended to general N -input logic gate and design the most efficient space response L'Ompactors according to the characteristies of output sequence from CUT. The prolxlsed design algorithm is implemented by C language on a SUN SPARC Workstation, and some experiment results of the simulation applied to ISCAS'85 benchmark circuits with pseudo random patterns generated bv LFSR( Linear Feedback Shift Register) show the efficiency and validity of the proposed design algorithm.