• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.533-534
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• 2006

This paper presents the architecture design of a high-speed, low-complexity 128-point radix-$2^4$ FFT processor for ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using 2-parallel data-path scheme and single-path delay-feedback (SDF) structure. This paper presents the key ideas applied to the design of high-speed, low-complexity FFT processor, especially that for achieving high throughput rate and reducing hardware complexity. The proposed FFT processor has been designed and implemented with the 0.18-m CMOS technology in a supply voltage of 1.8 V. The throughput rate of proposed FFT processor is up to 1 Gsample/s while it requires much smaller hardware complexity.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.4
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• pp.243-248
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• 2011

A FFT/IFFT processor is the key component for orthogonal frequency division multiplexing (OFDM) systems based IEEE 802.11n wireless local area network (WLAN). There exists many radix algorithms according to the structure of butterfly as FFT sub-module, each has the pros and cons on hardware complexity. Here, mixed radix algorithms for 64 and 128 FFT/IFFT processors are proposed, which reduce hardware complexity by using mixture of radix-23 and radix-4 algorithms. The proposed algorithm finish calculation within 3.2${\mu}s$ in order to meet IEEE 802.11n standard requirements and it has less hardware complexity compared with conventional algorithms.

• Journal of applied mathematics & informatics
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• v.20 no.1_2
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• pp.637-645
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• 2006

An adaptive algorithm for reducing the hardware complexity is presented. This paper proposes a simplified LMS algorithm for the adaptive system and analyzes its convergence characteristics mathematically. An objective of the proposed algorithm is to reduce the hardware complexity. In order to test the performances, it is applied to the echo canceller, and a program is described. The results from simulations show that the echo canceller adopting the proposed algorithm achieves almost the same performances as one adopting the NLMS algorithm. If an echo canceller is implemented with this algorithm, its computation quantities are reduced to the half as many as the one that is implemented with the LMS algorithm, without so much degradation of performances.

• Journal of Biomedical Engineering Research
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• v.28 no.3
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• pp.423-428
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• 2007

Programmable FIR filters are used in various signal processing tasks in medical ultrasound imaging, which are one of the major factors increasing hardware complexity. A widely used method to reduce the hardware complexity of a programmable FIR filter is to encode the filter coefficients in the canonic signed digit (CSD) format to minimize the number of nonzero digits (NZD) so that the multipliers for each filter coefficients can be replaced with fixed shifters and programmable multiplexers (PM). In this paper, a new structure for programmable FIR filters with a improved frequency response and a reduced hardware complexity compared to the conventional shift-and-add architecture using PM is proposed for implementing a very small portable ultrasound scanner. The CSD codes are optimized such that there exists at least one common nonzero digit between neighboring coefficients. Such common digits are then implemented with the same shifters. For comparison, synthesisable VHDL models for programmable FIR filters are developed based on the proposed and the conventional architectures. When these filters have the same hardware complexity, pass-band ana stop-band ripples of the proposed filter are lower than those of the conventional filter by about $0.01{\sim}0.19dB$ and by about $5{\sim}10dB$, respectively. For the same filter performance, the hardware complexity of the proposed architecture is reduced by more than 20% compare to the conventional SaA architecture.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.465-472
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• 2013

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.2
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• pp.485-499
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• 2021

Although non-binary low-density parity-check (NB-LDPC) codes have better error-correction capability than that of binary LDPC codes, their decoding complexity is significantly higher. Therefore, it is crucial to reduce the decoding complexity of NB-LDPC while maintaining their error-correction capability to adopt them for various applications. The extended min-sum (EMS) algorithm is widely used for decoding NB-LDPC codes, and it reduces the complexity of check node (CN) operations via message truncation. Herein, we propose a low-cost CN processing method to reduce the complexity of CN operations, which take most of the decoding time. Unlike existing studies on low complexity CN operations, the proposed method employs quick selection algorithm, thereby reducing the hardware complexity and CN operation time. The experimental results show that the proposed selection-based CN operation is more than three times faster and achieves better error-correction performance than the conventional EMS algorithm.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.4
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• pp.45-51
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• 2009

A hardware implementation of Hilbert transform is indespensible element in DSP system, but it suffers form a high complexity of system level hardware resulted in a large amount of the used gate. In this paper, we implemented the Hilbert transformer using MAG algorithm that reduces the complexity of hardware.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.168-176
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• 1996

This paper presetns a 2-D DCT architecture adopting accurac y compensator for reducing the hardware complexity and increasing processing speed in VL\ulcornerSI implementation. In the application fields such as moving pictures experts group (MPEG) and joint photographic experts group (JPEG), 2-D DCT processor must be implemented precisely enough to meet the accuracy specifications of the ITU-T H.261. Almost all of 2-D DCT processors have been implemented using many multiplications and accumulations of matrices and vectors. The number of multiplications and accumulations seriously influence on comlexity and speed of 20D DCT processor. In 2-D DCT with fixed-point calculations, the computation bit width must be sufficiently large for the above accuracy specifications. It makes the reduction of hardware complexity hard. This paper proposes the accuracy compensator which compensates the accuracy of the finite word length calculation. 2-D DCT processor with the proposed accuracy compensator shows fairly reduced hardware complexity and improved processing speed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.118-125
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• 2016

This paper presents a new high-efficient algorithm and architecture for an elliptic curve cryptographic processor. To reduce the computational complexity, novel modified Lopez-Dahab scalar point multiplication and left-to-right algorithms are proposed for point multiplication operation. Moreover, bit-serial Galois-field multiplication is used in order to decrease hardware complexity. The field multiplication operations are performed in parallel to improve system latency. As a result, our approach can reduce hardware costs, while the total time required for point multiplication is kept to a reasonable amount. The results on a Xilinx Virtex-5, Virtex-7 FPGAs and VLSI implementation show that the proposed architecture has less hardware complexity, number of clock cycles and higher efficiency than the previous works.

• Transactions on Electrical and Electronic Materials
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• v.18 no.6
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• pp.320-322
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• 2017

In this paper, a high-performance, low-area gradient-magnitude calculator architecture is proposed, based on approximate image processing. To reduce the computational complexity of the gradient-magnitude calculation, vector properties, the symmetry axis, and common terms were applied in a hardware-resource-shared architec-ture. The proposed gradient-magnitude calculator was implemented using an Altera Cyclone IV FPGA (EP4CE115F29) and the Quartus II v.16 device software. It satisfied the output-data quality while reducing the logic elements by 23% and the embedded multipliers by 76%, compared with previous work.