• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.69-77
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• 2004

An efficient board-level interconnect test algorithm is proposed considering both the ground bounce effect and the delay fault detection. The proposed algorithm is capable of IEEE 1149.1 interconnect test, negative ground bounce effect prevention, and also detects delay faults as well. The number of final test pattern set is not much different with the previous method, even our method enables to detect the delay faults in addition to the abilities the previous method guarantees.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.7
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• pp.1065-1073
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• 1999

This paper analyzed the ground bounce caused by the power plane resonance in the multilayered printed circuit board(PCB) using the Haar-wavelet-based Multiresolution Time-Domain (MRTD). In conventional Finite-Difference Time-Domain(FDTD), the highly fine vertical cell is needed to represent the distance between $V_{cc}$ plane and ground plane since the two planes are very close. Therefore the time step $\Deltat$ must be very small to satisfy the stability condition. As a result, a large number of iterations are needed to obtain the response in wanted time. For this problem, this paper showed that the computation time can be reduced by application of the MRTD method. The results obtained by the MRTD agree very well with those by FDTD method and analytic solutions. In conclusion, this paper proved the efficiency and accuracy of MRTD method for analyzing the EMI/EMC problems in PCB.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.134-138
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• 2008

We present a power gating turn-on mechanism that digitally suppresses ground-bounce noise in ultra-deep submicron technology. Initially, a portion of the sleep transistors are switched on in a pseudo-random manner and then they are all turned on fully when VVDD is above a certain reference voltage. Experimental results from a realistic test circuit designed in 65nm bulk CMOS technology show the potential of our approach.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.42-45
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• 2002

A low power SDRAM output buffer with reduced power line noise and feedthrough current is presented. In multi I/O SDRAM output buffer, feedthrough current as well as the corresponding power dissipation are reduced utilizing proposed undershoot protection circuits. Ground bounce is minimized by the pull down driver using intelligent feedback scheme. Ground bounce noise is reduced by 66.3% and instantaneous and average power are reduced by 27.5% and 11.4%, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.2 s.117
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• pp.199-205
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• 2007

In this paper, a novel hexagonal-shaped electromagnetic bandgap(EBG) power plane for the suppression of the ground bounce noise(GBN) in high-speed circuits is proposed. The proposed structure consists of hexagonal-shaped unit cells and detoured bridges connecting the unit cells. The hexagonal-shaped unit cells could omni-directionally suppress the GBN in digital circuits. The fabricated power plane's omni-directional -30 dB suppression bandwidth is from 330 MHz to 5.6 GHz. Then the proposed structure suppresses electromagnetic interference(EMI) caused by the GBN within the stopband. As a result, the proposed structure is expected to be conducive solving EMI problem in high-speed circuits.

• Journal of electromagnetic engineering and science
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• v.5 no.4
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• pp.183-188
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• 2005

A simple microwave backscattering model for vegetation canopies on earth surfaces is developed in this study. A natural earth surface is modeled as a two-layer structure comprising a vegetation layer and a ground layer. This scattering model includes various scattering mechanisms up to the first-order multiple scattering( double-bounce scattering). Radar backscatter from ground surface has been modeled by the polarimetric semi-empirical model (PSEM), while the backscatter from the vegetation layer modeled by the vector radiative transfer model. The vegetation layer is modeled by random distribution of mixed scattering particles, such as leaves, branches and trunks. The number of input parameters has been minimized to simplify the scattering model. The computation results are compared with the experimental measurements, which were obtained by ground-based scatterometers and NASA/JPL air-borne synthetic aperture radar(SAR) system. It was found that the scattering model agrees well with the experimental data, even though the model used only ten input parameters.

• 한국ITS학회:학술대회논문집
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• v.2007 no.10
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• pp.334-337
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• 2007

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.149-153
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• 1999

As VLSI technology advances rapidly, the operating frequency of digital systems becomes very fast. In such a high-speed system, there are many factors that threaten signal integrity. The noise sources in digital system include the noises in power supply, ground bounce and packaging media and distortions on single and multiple transmission lines. This paper will present a technology survey useful in the design of Gigabit interconnection systems. Some case studies have been constructed which show the lossy transmission line effect of skin effect. dielectric loss, with backplane connectors using the theoretical and practical conditions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.1
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• pp.140-145
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• 2005

The existing analytical expression for the voltage between the power and ground plane consist of metal-dielectric-metal board is expressed in the two dimensional infinite series. To reduce the computation time, the two dimensional infinite series is converted to the one dimensional infinite series using the summation formula of Fourier series. We applied these equations to the analysis of voltage between the $9‘{\times}4'$ size power-ground plane. The derived one dimensional infinite series shows the more rapid convergency and the more accurate result than the two dimensional infinite series. This equation can be applied to the power-ground plane analysis which needs a lot of the repeating computation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.79-84
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• 2008

Switching speeds increase in both frequency and the transition rate of edges. Inadequate forecast for simultaneous switching signals may cause designing the power planes without sufficient current capability. The delay of critical signals in a chip can be therefore inadvertently increased and the situation makes it hard to debug issues. It is important to find the degree of increased switching during the debugging or chip characterization phases. This paper proposes the interpolation method to predict the switching density in a design. The interpolation was achieved by utilizing the dependencies between switching frequency and the delay appeared in a ring oscillator. The ring oscillator was primarily used to accumulate the effects of the ground bounce by higher switching. The result of interpolation was demonstrated using DongBu Hitec 0.18um CMOS technology.