• Journal of The Korean Digital Architecture Interior Association
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• v.5 no.2
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• pp.21-28
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• 2005

The main purpose of this paper is to look into the relationship between pavilion and exhibit in Rodin Gallery. Rodin Gallery is intended to accommodate The Gates of Hell and The Burghers of Calais, two materpieces by the French sculptor Auguste Rodin. In order to retain Rodin's intent, the museum designed by KPF is constructed primarily of glass, which maximizes natural light and minimizes shadows. Thematically, the Glass Pavilion was designed to provide a place of relaxation in a highly urban environment.

• KCID journal
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• v.9 no.1
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• pp.38-47
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• 2002

The Lake Sihwa gradually changes from freshwater lake to saline lake due to inflow of seawater by sluice gates . The changes of lake water are closely related to characteristic and distribution of turbidity and suspended matter. During the period April-Ma

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.7
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• pp.844-850
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• 1988

In this paper, the implementation of optical parallel boolean logic gates using two Liquid Crystal TVs is described. Based on theory of polarization modulation, two Liquid Crystal TVs are arranged in tandem and parallel to perform optical logic operations. Experimental results of binary image using two Liquid Crystal TVs are presented.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.863-866
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• 1999

In this paper, we designed a Viterbi decoder with constraint length K=7, code rate R=1/2, encoder generator polynomial (171, 133)$_{8}$. This decoder makes use of 3-bit soft decision. We designed the Viterbi decoder using VHDL. We employed conventional logic circuit instead of ROM for branch metric units(BMUs) to reduce the number of gates. We adopted fully parallel structures for add-compare-select units(ACSUs). The size of the designed decoder is about 200, 000 gates.s.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.9
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• pp.1378-1385
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• 1990

In this paper we propose a model which can predict well the logical errors come from the charge redistribution in domino gates. In this model the effect of the intrinsic capacitance between gate and channel of MOSFET's is considered. This effect is more important than the parasitic capacitance effect. The error by the proposed model is only 8% of that by the currently used model. This model can be used as a guide-line in the design of domino circuits.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.1084-1087
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• 2000

This paper presents a new approach to evaluate the maximum number of simultaneous switching gates of a given combinational circuit. The new approach is based on an iterative method proposed by Sinogi et al. and applies a simulated annealing strategy to search jot a new solution. The experimental evaluation using ISCAS’85 benchmark circuits shows that the proposed approach has attained an excellent improvement compared with other rotated methods including the iterative method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.3 s.333
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• pp.43-50
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• 2005

In this paper, quaternary logic gates using Down literal circuit(DLC) has been designed, and then synchronous Quaternary un/down counter using those gates has been proposed The proposed counter consists of T-type quaternary flip flop and 1-of-2 threshold-t MUX, and T-type quaternary flip flop consists of D-type quaternary flip flop and quaternary logic gates(modulo-4 addition gates, Quaternary inverter, identity cell, 1-of-4 MUX). The simulation result of this counter show delay time of 10[ns] and power consumption of 8.48[mW]. Also, assigning the designed counter to MVL(Multiple-valued Logic) circuit, it has advantages of the reduced interconnection and chip area as well as easy expansion of digit.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.112-118
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• 2015

Conventional synchronous circuits cannot keep the circuit performance, and cannot even guarantee correct operations under the influence of PVT variations and aging effects in the nanometer regime. Therefore, in this paper, a DI (delay insensitive) design based NCL (Null Convention Logic) design methodology with a very simple design structure has been used to design digital systems, which is one of well-known asynchronous design methods robust to various variations and does not require any timing analysis. Because circuit-level structures of conventional NCL gates have weakness of low speed, high area overhead or high wire complexity, this paper proposes a new lNCL gates designed at the transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate libraries have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption using a asynchronous multiplier implemented in dongbu 0.11um CMOS technology.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.1
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• pp.29-36
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• 2016

Recently a new class of quantum gate called $NCV-{\mid}v_1$ > library with low cost realizable potentialities is being watched with keen interest. The $NCV-{\mid}v_1$ > MCT gate is composed of AND cascaded-$CV-{\mid}v_1$ > gates to control the target qudit and its adjoint gates to erase junk ones. This paper presents a new symmetrical duality library named $NCV^{\dag}-{\mid}v_1$ > library corresponding to $NCV-{\mid}v_1$ > library. The new $NCV^{\dag}-{\mid}v_1$ > library can be operated on OR logic under certain conditions. By using both the $NCV-{\mid}v_1$ > and $NCV^{\dag}-{\mid}v_1$ > libraries it is possible to realize MPMCT gates, SOP and POS type synthesis of quantum logic circuits with extremely low cost, and expect dual gate property caused by different operational attributes with respect to forward and backward operations.

• Journal of Korean Society of Water and Wastewater
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• v.25 no.6
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• pp.825-837
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• 2011

Seonakdong river consists of stagnant sections whose flowrate is controlled by the Daejeo and Noksan gates. As a result, there is not a minimum flow during normal times. The Daejeo and Noksan gates are located at the upstream head and the downstream end of Seonakdong river, respectively. Seonakdong river is an estuarine tributary of Nakdong river, which is a reservoir-like river used for agricultural irrigation, with the gate at the estuary of the river to prevent the intrusion of saline. Since the construction of the water gates, the water quality of the river has become degraded. This could also be due to the internal loading of pollutants, especially nutrients, from the sediments of the river because of the elongated detention time by the water gates. This study was thus conducted for the purpose of evaluating the current hydrologic-cycle system and providing measures for the rehabilitation of the hydrologic cycle. In this research, the daily outflow in Seonakdong River was simulated using the SWAT and SWMM models, and the water quality concentration including BOD, SS, TN, and TP were analyzed. The possibility of the application of SWAT-SWMM hybrid simulation was determined through the verification of both models. The error analysis shows that the results of both SWAT and SWAT-SWMM simulations make good agreements with those of field observations. For the single simulation results of SWAT, $R^{2}$ and NSE are 0.758, 0.511, respectively. For the hybrid simulation results of SWAT-SWMM, those are 0.880, 0.452, which means that the hybrid simulation can give more accurate results for the watershed where both the agricultural and urban areas exist.