• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.2
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• pp.297-305
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• 2000

It is observed that the initial properties and degradation characteristics on plasma of n/p-MOSFET with polycide and poly-Si as different gate materials under F-N stress and hot electron stress are affected by metal AR(Antenna Ratio) during plasma process. Compared to that of MOS devices with poly-Si gate material, reliability properties on plasma of MOS devices with polycide gate material are improved. This can be explained by that fluorine of tungsten polycide process diffuses through poly-Si into gate oxide and results in additional oxide thickness. The fact that MOS devices with polycide gate material can reduce damages of plasma process shows possibility that polycide gate material can be used as gate material for next generation MOS devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.2
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• pp.83-87
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• 2020

In this letter, we propose and analyze a new asymmetric structure that can be used for next-generation power semiconductor devices. We compare and analyze the electrical characteristics of the proposed device with respect to those of symmetric devices. The proposed device has a p-emitter on the right side of the cell. The peak electric field is reduced by the shielding effect caused by the p-emitter structure. Consequently, the breakdown voltage is increased. The proposed asymmetric structure has an approximately 100% higher Baliga's figure of merit (~94.22 MW/㎠) than the symmetric structure (~46.93 MW/㎠), and the breakdown voltage of the device increases by approximately 70%.

• Transactions on Electrical and Electronic Materials
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• v.18 no.4
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• pp.195-198
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• 2017

This research analyzed the electrical characteristics of an 80 V optimal trench power MOSFET (metal oxide field effect transistor) for mobile applications. The power MOSFET is a fast switching device in fields with low voltage(<100 V) such as mobile application. Moreover, the power MOSFET is a major carrier device that is not minor carrier accumulation when the device is turned off. We performed process and device simulation using TCAD tools such as MEDICI and TSUPREM. The electrical characteristics of the proposed trench gate power MOSFET such as breakdown voltage and on resistance were compared with those of the conventional power MOSFET. Consequently, we obtained breakdown voltage of 100 V and low on resistance of $130m{\Omega}$. The proposed power MOSFET will be used as a switch in batteries of mobile phones and note books.

• Korean Journal of Materials Research
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• v.1 no.3
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• pp.125-131
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• 1991

Boron penetration phenomenon of $p^{+}$ silicon gate with as-deposited amorphous or polycrystalline Si upon high temperature annealing was investigated using high frequency C-V (Capacitance-Volt-age) analysis, CCST(Constant Current Stress Test), TEM(Transmission Electron Microscopy) and SIMS(Secondary Ion Mass Spectroscopy), C-V analysis showed that an as-deposited amorphous Si gate resulted in smaller positive shifts in flatband voltage compared wish a polycrystalline Si gate, thus giving 60-80 percent higher charge-to-breakdown of gate oxides. The reduced boron penetration of amorphous Si gate may be attributed to the fewer grain boundaries available for boron diffusion into the gate oxide and the shallower projected range of $BF_2$ implantation. The relation between electron trapping rate and flatband voltage shift was also discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.194-195
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• 2006

Aluminum oxide films directly grown on n-type 6H-SiC(0001) substrates were fabricated by RF magnetron sputtering system. Metal-insulator-semiconductor(MIS) C-V properties with aluminum oxide thin films showed hysteresis and f1at band voltage shift. The dielectric constant of the film calculated from the capacitance at the accumulation region was about 5. Typical gate leakage current density of film at room temperature was the order of $10^{-9}\;A/cm^2$ at the range of within 2MV/cm. The breakdown did not occur at the film within the measurement range.

• Proceedings of the KIEE Conference
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• 1998.11c
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• pp.737-739
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• 1998

Gate insulators using various fluoride films were investigated for thin film transistor applications. Conventional oxide containing materials exhibited high interface states, high $D_{it}$ gives an increased threshold voltage and poor stability of TFT. To improve TFT performances, we must reduce interface trap charge density between Si and gate insulator. In this paper, we investigated gate insulators such as such as $CaF_2$, $SrF_2$, $MgF_2$ and $BaF_2$. These materials exhibited an improvement in lattice mismatch, difference in thermal expansion coefficient, and electrical stability MIM and MIS devices were employed for an electrical characterization and structural property examination. Among the various fluoride materials, $CaF_2$ film showed an excellent lattice mismatch of 0.737%, breakdown electric field higher than 1.7MV/cm and leakage current density of $10^{-6}A/cm^2$. This paper probes a possibility of new gate insulator material for TFT application.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.265-270
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• 2017

4H-SiC has attracted attention for high-power and high-temperature metal-oxide-semiconductor field-effect transistors (MOSFETs) for industrial and automotive applications. The gate oxide in the 4H-SiC MOS system is important for switching operations. Above $1000^{\circ}C$, thermal oxidation initiates $SiO_2$ layer formation on SiC; this is one advantage of 4H-SiC compared with other wide band-gap materials. However, if post-deposition annealing is not applied, thermally grown $SiO_2$ on 4H-SiC is limited by high oxide charges due to carbon clusters at the $SiC/SiO_2$ interface and near-interface states in $SiO_2$; this can be resolved via low-temperature deposition. In this study, low-temperature $SiO_2$ deposition on a Si substrate was optimized for $SiO_2/4H-SiC$ MOS capacitor fabrication; oxide formation proceeded without the need for post-deposition annealing. The $SiO_2/4H-SiC$ MOS capacitor samples demonstrated stable capacitance-voltage (C-V) characteristics, low voltage hysteresis, and a high breakdown field. Optimization of the treatment process is expected to further decrease the effective oxide charge density.

• Journal of IKEEE
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• v.20 no.3
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• pp.220-225
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• 2016

In this paer, low on-resistance and high-power trench gate MOSFET (Metal-Oxide-Silicon Field Effect Transistor) incorporating current sensing FET (Field Effect Transistor) is proposed and evaluated. The trench gate power MOSFET was fabricated with $0.6{\mu}m$ trench width and $3.0{\mu}m$ cell pitch. Compared with the main switching MOSFET, the on-chip current sensing FET has the same device structure and geometry. In order to improve cell density and device reliability, self-aligned trench etching and hydrogen annealing techniques were performed. Moreover, maintaining low threshold voltage and simultaneously improving gate oxide relialility, the stacked gate oxide structure combining thermal and CVD (chemical vapor deposition) oxides was adopted. The on-resistance and breakdown voltage of the high density trench gate device were evaluated $24m{\Omega}$ and 100 V, respectively. The measured current sensing ratio and it's variation depending on the gate voltage were approximately 70:1 and less than 5.6 %.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.431-437
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• 1998

In this paper, we have investigated the electrical properties of ultra-thin nitrided oxide(NO) and re-oxidized nitrided oxide(ONO) films that are considered to be promising candidates for replacing conventional silicon dioxide film in ULSI level integration. Especially, we have studied a variation of I-V characteristics, gate voltage shift, and time-dependent dielectric breakdown(TDDB) of thin layer NO and ONO film depending on nitridation and reoxidation time, respectively, and measured a variation of leakage current and charge-to-breakdown(Q$\_bd$) of optimized NO and ONO film depending on ambient temperature, and then compared with the properties of conventional SIO$\_2$. From the results, we find that these NO and ONO thin films are strongly influenced by process time and the optimized ONO film shows superior dielectric characteristics, and (Q$\_bd$) performance over the NO film and SIO$\_2$, while maintaining a similar electric field dependence compared with NO layer.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.6
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• pp.558-569
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• 2017

In this paper, a 256Kb EEPROM IP aimed at battery applications using a single supply of 1.5V which is embedded into an MCU is designed. In the conventional cross-coupled VPP (boosted voltage) charge pump using a body-potential biasing circuit, cross-coupled PMOS devices of 5V in it can be broken by the junction or gate oxide breakdown due to a high voltage of 8.53V applied to them in exiting the program or erase mode. Since each pumping node is precharged to the input voltage of the pumping stage at the same time that the output node is precharged to VDD in the cross-coupled charge pump, a high voltage of above 5.5V is prevented from being applied to them and thus the breakdown does not occur. Also, all erase, even program, odd program, and all program modes are supported to reduce the times of erasing and programming 256 kilo bits of cells. Furthermore, disturbance test time is also reduced since disturbance is applied to all the 256 kilo bits of EEPROM cells at once in the cell disturb test modes to reduce the cell disturbance testing time. Lastly, a CG driver with a short disable time to meet the cycle time of 40ns in the erase-verify-read mode is newly proposed.