• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.832-835
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• 2001

We report the structural and electrical properties of hafnium oxide (HfO$_2$) films with tungsten silicide (WSi$_2$) metal gate. In this study, HfO$_2$thin films were fabricated by oxidation of sputtered Hf metal films on Si, and WSi$_2$was deposited directly on HfO$_2$by LPCVD. The hysteresis windows in C-V curves of the WSi$_2$HfO$_2$/Si MOS capacitors were negligible (<20 mV), and had no dependence on frequency from 10 kHz to 1 MHz and bias ramp rate from 10 mV to 1 V. In addition, leakage current was very low in the range of 10$^{-9}$ ~10$^{-10}$ A to ~ 1 V, which was due to the formation of interfacial hafnium silicate layer between HfO$_2$and Si. After PMA (post metallization annealing) of the WSi$_2$/HfO$_2$/Si MOS capacitors at 500 $^{\circ}C$ EOT (equivalent oxide thickness) was reduced from 26 to 22 $\AA$ and the leakage current was reduced by approximately one order as compared to that measured before annealing. These results indicate that the effect of fluorine diffusion is negligible and annealing minimizes the etching damage.

• Transactions on Electrical and Electronic Materials
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• 제4권6호
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• pp.32-37
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• 2003

In this paper, the trap characteristics of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4nm and 814nm, which have the gate area 10$\^$-3/ $\textrm{cm}^2$. The stress induced leakage currents will affect data retention, and the stress current and transient current is used to estimate to fundamental limitations on oxide thicknesses.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.245-251
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• 2013

The effect of band-to-band tunneling (BTBT) leads to an obvious increase of the leakage current of junctionless (JL) transistors in the OFF state. In this paper, we propose an effective method to decline the influence of BTBT with the example of n-type double gate (DG) JL metal-oxide-semiconductor field-effect transistors (MOSFETs). The leakage current is restrained by changing the geometrical shape and the physical dimension of the gate of the device. The optimal design of the JL MOSFET is indicated for reducing the effect of BTBT through simulation and analysis.

• 대한전자공학회논문지SD
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• 제41권11호
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• pp.7-13
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• 2004

두께가 약 3 nm 인 게이트 산화막을 갖는 P 및 NMOSFET를 제조하여 높은 압력 (5 atm.)의 중수소 및 수소 분위기에서 후속 열처리를 각각 행하여 중수소 효과(동위원소 효과)를 관찰하였다. 소자에 대한 스트레스는 -2.5V ≤ V/sub g/ ≤-4.0V 범위에서 100℃의 온도를 유지하며 진행되었다. 낮은 스트레스 전압에서는 실리콘 계면에 존재하는 정공에 의하여 게이트 산화막의 열화가 진행되었다. 그러나 스트레스 전압을 증가시킴으로써 높은 에너지를 갖는 전자에 의한 계면 결함 생성이 열화의 직접적인 원인이 됨을 알 수 있었다. 본 실험조건에서는 실리콘 계면에서 phonon 산란이 많이 발생하여 impact ionization에 의한 "hot" 정공의 생성은 무시할 수 있었다. 중수소 열처리를 행함으로써 수소 열처리에 비해 소자의 파라미터 변화가 적었으며, 게이트 산화막의 누설전류도 억제됨이 확인되었다. 이러한 결과로부터 impact ionization이 발생되지 않을 정도의 낮은 스트레스 전압동안 발생하는 게이트 산화막내 결함 생성은 수소 결합과 직접적인 관계가 있음을 확인하였다.

• 반도체디스플레이기술학회지
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• 제16권1호
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• pp.97-101
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• 2017

In this paper, IGZO thin film transistor (TFT) was fabricated with cross-linked Poly (4-vinylphenol) (PVP) gate dielectric for flexible, transparent display applications. The PVP is one of the candidates for low-temperature gate insulators. MIM structure was fabricated to measure the leakage current and evaluate the insulator properties according to the annealing temperature. Low leakage current ( <0.1nA/cm2 @ 1MV/cm ) was observed at $200^{\circ}C$ annealing condition and decreases much more as the annealing temperature increases. The electrical characteristics of IGZO TFT such as subthreshold swing, mobility and ON/OFF current ratio were also improved, which shows that the performance of IGZO TFTs with PVP can be enhanced by reducing the amount of incomplete crosslinking in PVP.

• 한국전기전자재료학회논문지
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• 제16권12S호
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• pp.1175-1180
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• 2003

Transformer Coupled Plasma Chemical Vapor Deposited (TCP-CVD) silicon nitride (SiNx) is widely used as a gate dielectric material for thin film transistors (TFT). This paper reports the SiNx films, grown by TCP-CVD at the low temperature (30$0^{\circ}C$). Experimental investigations were carried out for the optimization o(SiNx film as a function of $N_2$/SiH$_4$ flow ratio varying ,3 to 50 keeping rf power of 200 W, This paper presents the dielectric studies of SiNx gate in terms of deposition rate, hydrogen content, etch rate and leakage current density characteristics lot the thin film transistor applications. And also, this work investigated means to decrease the leakage current of SiNx film by employing $N_2$ plasma treatment. The insulator layers were prepared by two step process; the $N_2$ plasma treatment and then PECVD SiNx deposition with SiH$_4$, $N_2$gases.

• Transactions on Electrical and Electronic Materials
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• 제11권2호
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• pp.49-53
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• 2010

Microstructural origins of leakage current and physical degradation during operation in product-quality AlGaN/GaN high electron mobility transistor (HEMT) devices were investigated using photon emission microscopy (PEM) and transmission electron microscopy (TEM). AlGaN/GaN HEMTs were fabricated with metal organic chemical vapor deposition on semi-insulating SiC substrates. Photon emission irregularity, which is indicative of gate leakage current, was measured by PEM. Site specific TEM analysis assisted by a focused ion beam revealed the presence of threading dislocations in the channel below the gate at the position showing strong photon emissions. Observation of electrically degraded devices after life tests revealed crack/pit shaped defects next to the drain in the top AlGaN layer. The morphology of the defects was three-dimensionally investigated via electron tomography.

• 반도체디스플레이기술학회지
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• 제9권4호
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• pp.1-5
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• 2010

The PVA (poly-vinyl alcohol) insulators were spun coated onto ITO coated glass substrates with the capacitors of Glass/ITO/PVA/Al structure. The effects of PVA concentrations (3.0, 4.0 and 5.0 wt%) on the morphology and electrical properties of the films were investigated. As the concentration of PVA increased from 3.0 to 5.0 wt%, the leakage current of device decreased from 17.1 to 0.23 pA. From the AFM measurement, the RMS value decreased with increasing PVA concentration, showing the improvement of insulator film roughness. The capacitances of the films with PVA concentrations of 4.0 and 5.0 wt% were about 28.1 and 24.2 nF, respectively. The lowest leakage current of 1.77 PA was obtained at the film thickness of 117.5 nm for the device with fixed PVA concentration of 5.0 wt%.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권2호
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• pp.116-119
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• 2000

A hybrid SOI bipolar-mode field effect transistor (BMFET) is proposed to improve the current gain. The device characteristics are analyzed and verified numerically for BMFET mode, DMOS mode, and hybrid mode by MEDICI simulation. The proposed SOI BMFET exhibits 30 times larger current gain in hybrid-mode operation by connecting DMOS gate to the p+ gate of BMFET structure as compared with the conventional structure without sacrifice of breakdown voltage and leakage current characteristics. This is due to the DMOS-gate-induced hybrid effect that lowers the barrier of p-body and reduces the charge in p-body.

• 전기학회논문지
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• 제57권2호
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• pp.235-238
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• 2008

This paper explores 28 nm MOSFET design for LSTP(Low Standby Power) applications using TCAD(Technology Computer Aided Design) simulation. Simulated results show that the leakage current of the MOSFET is increasingly dominated by GIDL(Gate Induced Drain Leakage) instead of a subthreshold leakage as the Source/Drain extension doping increases. The GIDL current can be reduced by grading lateral abruptness of the drain at the expense of a higher Source/Drain series resistance. For 28 nm MOSFET suggested in ITRS, we have shown Source/Drain design becomes even more critical to meet both leakage current and performance requirement.