• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.343-347
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• 2004

High oxidation temperature of SiC shows a tendency of carbide formation at the interface which results in poor MOSFET transfer characteristics. Thus we developed oxidation processes in order to get low interface charge densities. N-type 6H-SiC MOS capacitors were fabricated by different oxidation processes: dry, wet, and dry­reoxidation. Gate oxidation and Ar anneal temperature was $1150^{\circ}C.$ Ar annealing was performed after gate oxidation for 30 minutes. Dry-reoxidation condition was $950^{\circ}C,$ H2O ambient for 2 hours. Gate oxide thickness of dry, wet and dry-reoxidation samples were 38.0 nm, 38.7 nm, 38.5 nm, respectively. Mo was adopted for gate electrode. To investigate quality of these gate oxide films, high frequency C- V measurement, gate oxide leakage current, and interface trapped charge densities (Dit) were measured. The interface trapped charge densities (Dit) measured by conductance method was about $4\times10^{10}[cm^{-1}eV^{-1}]$ for dry and wet oxidation, the lowest ever reported, and $1\times10^{11}[cm^{-1}eV^{-1}]$ for dry-reoxidation

• 전자공학회논문지A
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• 제31A권6호
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• pp.107-116
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• 1994

In this paper, The electrical properties of MOS capacitors and transistoras with gate of in-situ doped amorphous Si and poly Si doped by POCI$_3$. Under constant current F-N stress, MOS capacitors with in-situ doped amorphous Si gate have shown the best resistance to degradation in reliabilty properties such as increase of leakage current, shift of gate voltage (V$_{g}$). shift of flat band voltage (V$_{fb}$) and charge to breakdown(Q$_{bd}$). Also, MOSFETs with in-situ doped amorphous Si gate have shown to have less degradation in transistor properties such as threshold voltage, transconductance and drain current. These improvements observed in MOS devices with in-situ doped amorphous Si gate is attributed to less local thinning spots at the gate/SiO$_2$ interface, caused by the large grain size and the smoothness of the surface at the gate/SiO$_2$ interface.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2017년도 춘계학술대회 논문집
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• pp.138-138
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• 2017

차세대 CMOS 소자의 지속적인 고직접화를 위해서는 높은 gate capacitance와 낮은 gate leakage current를 확보를 위한, 적절한 metal gate electrode와 high-k dielectric 물질의 개발이 필수적으로 요구된다. 특히, gate dielectric으로 적용하기 위한 다양한 high-k dielectric 물질 후보군 중에서, 높은 dielectric constant와, 낮은 leakage current, 그리고 Si과의 우수한 열적 안정성을 가지는 Zr silicates 또는 Hf silicates(ZrSiO4와 HfSiO4) 물질이 높은 관심을 받고 있으며, 이를 원자층 증착법을 통해 구현하기 위한 노력들이 있어왔다. 그러나, 현재까지 보고된 원자층 증착법을 이용한 Zr silicates 및 Hf silicates 공정의 경우, 개별적인 Zr(또는 Hf)과 Si precursor를 이용하여 ZrO2(또는 HfO2)과 SiO2를 반복적으로 증착하는 방식으로 Zr silicates 또는 Hf silicates를 형성하고 있어, 전체 공정이 매우 복잡해지는 문제점 뿐 아니라, gate dielectric 내에서 Zr과 Si의 국부적인 조성 불균일성을 야기하여, 제작된 소자의 신뢰성을 떨어뜨리는 문제점을 나타내왔다. 따라서, 본 연구에서는 이러한 문제점을 개선하기 위하여, 하나의 precursor에 Zr (또는 Hf)과 Si 원소를 동시에 가지고 있는 DNS-Zr과 DNS-Hf bimetallic precursor를 이용하여 새로운 ZrSiO4와 HfSiO4 ALD 공정을 개발하고, 그 특성을 살펴보고자 하였다. H2O와 O3을 reactant로 사용한 원자층 증착법 공정을 통하여, Zr:Si 또는 Hf:Si의 화학양론적 비율이 항상 일정한 ZrSiO4와 HfSiO4 박막을 형성할 수 있었으며, 이들의 전기적 특성 평가를 진행하였으며, dielectric constant 및 leakage current 측면에서 우수한 특성을 나타냄을 확인할 수 있었다. 이러한 결과를 바탕으로, bimetallic 전구체를 이용한 ALD 공정은 차세대 고성능 논리회로의 게이트 유전물질에 응용이 가능할 것으로 판단된다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 D
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• pp.1931-1933
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• 1999

In this paper, the current and voltage properties on the gate oxide film due to the variation of thickness are studied. The specimen is used for n-ch power MOSFET. It is shows the leakage current and current density characteristics due to the applied electric field when the oxide thickness is each $600[\AA],\;800[\AA]$ and $1000[\AA]$, respectively. We known that the leakage current is a little higher when the voltage as reverse bias contrast with forward bias in poly gate is applied. In order to experiment for AC properties is measured for capacitance characteristics. It is confirmed that the value of input capacitance have been a lot of influenced on $SiO_2$ thickness contrast with the value of output capacitance.

• 한국재료학회지
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• 제13권1호
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• pp.11-17
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• 2003

DC characteristics of recessed gate 4H-SiC MESFET were investigated using the device/circuit simulation tool, PISCES. Results of theoretical calculation were compared with the experimental data for the extraction of modeling parameters which were implemented for the prediction of DC and gate leakage characteristics at high temperatures. The current-voltage analysis using a fixed mobility model revealed that the short channel effect is influenced by the defects in SiC. The incomplete ionization models are found out significant physical models for an accurate prediction of SiC device performance. Gate leakage is shown to increase with the device operation temperatures and to decrease with the Schottky barrier height of gate metal.

• 한국산학기술학회논문지
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• 제22권2호
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• pp.810-818
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• 2021

ESS의 누설전류는 PCS(Power Control System)측 누설전류와 계통불평형 전류로 인한 누설전류로 구분되는데, PCS측의 누설전류는 정상 상태 운전 시, IGBT(Insulated Gate Bipolar Transistor) 스위칭의 전압 변화량과 IGBT와 방열판 사이에 존재하는 기생 커패시턴스에 의해 발생한다. 또한, 계통불평형 전류에 의한 누설전류는 불평형 부하로 인해 발생한 불평형 전류가 Yg-∆ 결선방식의 3각 철심이 적용된 태양광전원 연계형 변압기의 중성선을 통해 ESS로 유입된다. 따라서, 본 논문에서는 방열판 유도공식을 통해 산정한 기생 커패시턴스에 의하여 PCS측의 누설전류 발생 메커니즘을 제시하고 또한, 계통불평형에 의한 ESS측의 누설전류 발생 메커니즘을 제안한다. 이를 바탕으로, 배전계통 상용해석 프로그램인 PSCAD/EMTDC를 이용하여 배터리부, PCS부, AC전원부로 이루어진 PCS측의 누설전류 발생 메커니즘과 배전 계통부, 불평형 부하부, ESS부로 이루어진 계통불평형에 의한 ESS측의 누설전류 발생 메커니즘을 모델링하고, 누설전류의 특성을 평가한다. 상기의 모델링을 바탕으로 시뮬레이션을 수행한 결과, 외함의 저항과 접지저항의 크기에 따라 PCS측의 누설전류는 7[mA]에서 34[mA]로, 계통불평형에 의한 배터리 외함으로 흐르는 누설전류는 3.96[mA]에서 10.76[mA]로 증가하여 배터리측에 큰 영향을 미침을 알 수 있었다.

• 대한전자공학회논문지SD
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• 제38권6호
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• pp.390-397
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• 2001

GIDL(Gate-Induced Drain-Leakage)을 줄일 수 있는 새로운 구조의 ESD(Elevated Source Drain) MOSFET을 제안하고 분석하였다. 제안된 구조는 SDE(Source Drain Extension) 영역이 들려진 형태를 갖고 있어서 SDE 임플란트시 매우 낮은 에너지 이온주입으로 인한 저활성화(low-activation) 효과를 방지 할 수 있다. 제안된 구조는 건식 식각 및 LAT(Large-Angle-Tilted) 이온주입 방법을 사용하여 소오스/드레인 구조를 결정한다. 기존의 LDD MOSFET과의 비교 시뮬레이션 결과, 제안된 ESD MOSFET은 전류 구동능력은 가장 크면서 GIDL 및 DIBL(Drain Induced Barrier Lowering) 값은 효과적으로 감소시킬 수 있음을 확인하였다. GIDL 전류가 감소되는 원인으로는 최대 전계의 위치가 드레인 쪽으로 이동함에 따라 최대 밴드간 터널링이 일어나는 곳에서의 최대 전계값이 감소되기 때문이다.

• 전자공학회논문지A
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• 제30A권12호
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• pp.77-87
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• 1993

PMOSFETs were studied on the effect of Hot-Carrier induced drain leakage current (Gate-Induced-Drain-Leakage). The result turned out that change in Vgl(drain voltage where 1pA/$\mu$m of drain leadage current flows) was largest in the Channel-Hot-Hole(CHH) injection condition and next was in dynamic stress and was smallest in electron trapping (Igmax) condition under various stress conditions. It was analyzed that if electron trapping occurrs in the overlap region of gate and drain(G/D), it reduces GIDL current due to increment of flat-band voltage(Vfb) and if CHH is injected, interface states(Nit) were generated and it increases GIDL current due to band-to-defect-tunneling(BTDT). Especially, under dynamic stress it was confirmed that increase in GIDL current will be high when electron injection was small and CHH injection was large. Therefore as applying to real circuit, low drain voltage GIDL(BTDT) was enhaced as large as CHH Region under various operating voltage, and it will affect the reliablity of the circuit.

• Journal of Electrical Engineering and Technology
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• 제8권5호
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• pp.1157-1162
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• 2013

We proposed AlGaN/GaN high-electron-mobility transistors (HEMTs) using thermal oxidation for NiOx passivation. Auger electron spectroscopy, secondary ion mass spectroscopy, and pulsed I-V were used to study oxidation features. The oxidation process diffused Ni and O into the AlGaN barrier and formed NiOx on the surface. The breakdown voltage of the proposed device was 1520 V while that of the conventional device was 300 V. The gate leakage current of the proposed device was 3.5 ${\mu}A/mm$ and that of the conventional device was 1116.7 ${\mu}A/mm$. The conventional device exhibited similar current in the gate-and-drain-pulsed I-V and its drain-pulsed counterpart. The gate-and-drain-pulsed current of the proposed device was about 56 % of the drain-pulsed current. This indicated that the oxidation process may form deep states having a low emission current, which then suppresses the leakage current. Our results suggest that the proposed process is suitable for achieving high breakdown voltages in the GaN-based devices.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 D
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• pp.1965-1967
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• 1999

We have investigated the electrical characteristics of the poly-Si TFT's with the novel gate insulator structure. The gate insulator makes the offset region to reduce leakage current, and the electrical characteristics are obtained by employing Virtual Wafer Fab. simulator. As increases the gate insulator thickness above the offset region of this structure from $0{\AA}$ to $2000{\AA}$, the OFF state current at $V_G$=10V decrease by two orders in magnitude while ON state current doesn't decrease significantly. ON/OFF current ratios for conventional device and the proposed device with $2000{\AA}$ gate insulator thickness are $1.68{\times}10^5$ and $1.07{\times}10^7$, respectively.