• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.183-190
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• 2010

We propose an eFuse one-time programmable (OTP) memory cell based on a logic process, which is programmable by an external program voltage. For the conventional eFuse OTP memory cell, a program datum is provided with the SL (Source Line) connected to the anode of the eFuse going through a voltage drop of the SL driving circuit. In contrast, the gate of the NMOS program transistor is provided with a program datum and the anode of the eFuse with an external program voltage (FSOURCE) of 3.8V without any voltage drop for the newly proposed eFuse cell. The FSOURCE voltage of the proposed cell keeps either 0V or the floating state at read mode. We propose a clamp circuit for being biased to 0V when the voltage of FSOURCE is in the floating state. In addition, we propose a VPP switching circuit switching between the logic VDD (=1.8V) and the FSOURCE voltage. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's $0.15{\mu}m$ generic process is $359.92{\times}90.98{\mu}m^2$.

• Journal of Biomedical Engineering Research
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• v.25 no.4
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• pp.269-275
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• 2004

Different biological tissues have different values of electrical resistivity. In EIT (electrical impedance tomography), we try to provide cross-sectional images of a resistivity distribution inside an electrically conducting subject such as the human body mainly for functional imaging. However, it is well known that the image reconstruction problem in EIT is ill-posed and the quality of a reconstructed image highly depends on the measurement error. This requires us to develop a high-performance EIT system. In this paper, we describe the development of a 16-channel digital EIT system including a single constant current source, 16 voltmeters, main controller, and PC. The system was designed and implemented using the FPGA-based digital technology. The current source injects 50KHz sinusoidal current with the THD (total harmonic distortion) of 0.0029% and amplitude stability of 0.022%. The single current source and switching circuit reduce the measurement error associated with imperfect matching of multiple current sources at the expense of a reduced data acquisition time. The digital voltmeter measuring the induced boundary voltage consists of a differential amplifier, ADC, and FPGA (field programmable gate array). The digital phase-sensitive demodulation technique was implemented in the voltmeter to maximize the SNR (signal-to-noise ratio). Experimental results of 16-channel digital voltmeters showed the SNR of 90dB. We used the developed EIT system to reconstruct resistivity images of a saline phantom containing banana objects. Based on the results, we suggest future improvements for a 64-channel muff-frequency EIT system for three-dimensional dynamic imaging of bio-impedance distributions inside the human body.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.2
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• pp.810-818
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• 2021

A leakage current of ESS is classified mainly by the occurrence from a PCS(Power Conditioning System) section and an unbalanced grid current. The reason for the leakage current from the PCS section is a voltage change by IGBT (Insulated Gate Bipolar Transistor) switching and stray capacitance between the IGBT and heatsink. The leakage current caused by the grid unbalanced current flows to the ESS through the neutral line of grid-connected transformer for the ESS with a three limb iron type of Yg-wire connection. This paper proposes a mechanism for the occurrence of leakage current caused by stray capacitance, which is calculated using the heatsink formula, from the aspect of the PCS section and grid unbalance current. Based on the proposed mechanisms, this study presents the modeling of the leakage current occurrence using PSCAD/EMTDC S/W and evaluates the characteristics of leakage currents from the PCS section and grid unbalanced current. From the simulation result, the leakage current has a large influence on the battery side by confirming that the leakage current from the PCS is increased from 7[mA] to 34[mA], and the leakage current from an unbalanced load to battery housing is increased from 3.96[mA] to 10.76[mA] according to the resistance of the housings and the magnitude of the ground resistance.

• Journal of IKEEE
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• v.26 no.3
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• pp.422-429
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• 2022

A light sensor chip requires a small capacity eFuse (electrical fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) to trim analog circuits or set initial values of digital registers. In this paper, 128-bit eFuse OTP IP is designed using only 3.3V MV (Medium Voltage) devices without using 1.8V LV (Low-Voltage) logic devices. The eFuse OTP IP designed with 3.3V single MOS devices can reduce a total process cost of three masks which are the gate oxide mask of a 1.8V LV device and the LDD implant masks of NMOS and PMOS. And since the 1.8V voltage regulator circuit is not required, the size of the illuminance sensor chip can be reduced. In addition, in order to reduce the number of package pins of the illumination sensor chip, the VPGM voltage, which is a program voltage, is applied through the VPGM pad during wafer test, and the VDD voltage is applied through the PMOS power switching circuit after packaging, so that the number of package pins can be reduced.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.69-76
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• 2016

Current driving capability of MCT (MOS Controlled Thyristor) is determined by turn-off capability of conducting current, that is off-FET performance of MCT. On the other hand, having a good turn-on characteristics, including high peak anode current ($I_{peak}$) and rate of change of current (di/dt), is essential for pulsed power system which is one of major application field of MCTs. To satisfy above two requirements, careful control of on/off-FET performance is required. However, triple diffusion and several oxidation processes change surface doping profile and make it hard to control threshold voltage ($V_{th}$) of on/off-FET. In this paper, we have demonstrated the effect of $V_{th}$ adjustment ion implantation on the performance of MCT. The fabricated MCTs (active area = $0.465mm^2$) show forward voltage drop ($V_F$) of 1.25 V at $100A/cm^2$ and Ipeak of 290 A and di/dt of $5.8kA/{\mu}s$ at $V_A=800V$. While these characteristics are unaltered by $V_{th}$ adjustment ion implantation, the turn-off gate voltage is reduced from -3.5 V to -1.6 V for conducting current of $100A/cm^2$ when the $V_{th}$ adjustment ion implantation is carried out. This demonstrates that the current driving capability is enhanced without degradation of forward conduction and turn-on switching characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.265.2-265.2
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• 2016

Oxide thin film transistors (TFTs) have attracted considerable interest for gate diver and pixel switching devices of the active matrix (AM) liquid crystal display (LCD) and organic light emitting diode (OLED) display because of their high field effect mobility, transparency in visible light region, and low temperature processing below $300^{\circ}C$. Recently, oxide TFTs with polycrystalline In-Ga-O(IGO) channel layer reported by Ebata. et. al. showed a amazing field effect mobility of $39.1cm^2/Vs$. The reason having high field effect mobility of IGO TFTs is because $In_2O_3$ has a bixbyite structure in which linear chains of edge sharing InO6 octahedral are isotropic. In this work, we investigated the characteristics and the effects of oxygen partial pressure significantly changed the IGO thin-films and IGO TFTs transfer characteristics. IGO thin-film were fabricated by rf-magnetron sputtering with different oxygen partial pressure ($O_2/(Ar+O_2)$, $Po_2$)ratios. IGO thin film Varies depending on the oxygen partial pressure of 0.1%, 1%, 3%, 5%, 10% have been some significant changes in the electrical characteristics. Also the IGO TFTs VTH value conspicuously shifted in the positive direction, from -8 to 11V as the $Po_2$ increased from 1% to 10%. At $Po_2$ was 5%, IGO TFTs showed a high drain current on/off ratio of ${\sim}10^8$, a field-effect mobility of $84cm^2/Vs$, a threshold voltage of 1.5V, and a subthreshold slpe(SS) of 0.2V/decade from log(IDS) vs VGS.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.8
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• pp.752-758
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• 2004

This paper reports on the DC and RF characteristics of AlGaN/InGaN/GaN high electron-mobility transistors (HEMTs) grown by molecular beau epitaxy(MBE) on sapphire substrates. The devices with a 0.5 ${\mu}$m gate-length exhibited relatively flat transconductance(g$\_$m/), which results from the enhanced carrier confinement of the InGaN channel. The maximum drain current was 880 mA/mm with a peak g$\_$m/ of 156 mS/mm, an f$\_$T/ of 17.3 GHz, and an f$\_$MAX/ or 28.7 GHz. In addition to promising DC and RF results, pulsed I-V and current-switching measurements showed little dispersion in the unpassivated AlGaN/InGaN HEMTs. These results suggest that the addition of In to the GaN channel improves the electron transport characteristics as well as suppressing current collapse that is related to the surface trap states.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.269-275
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• 2003

Polysilicon-oxide-nitride-oxide-silicon(SONOS) transistors were fabricated by using 0.35${\mu}{\textrm}{m}$ complementary metal-oxide-semiconductor(CMOS) process technology to realize a low voltage programmable flash memory. The thickness of the tunnel oxide, the nitride, and the blocking oxide were 2.4nm, 4.0nm, and 2.5nm, respectively, and the cell area of the SONOS memory was 1.32$\mu$$m^2$. The SONOS device revealed a maximum memory window of 1.76V with a switching time of 50ms at 10V programming, as a result of the scaling effect of the nitride. In spite of scaling of nitride thickness, memory window of 0.5V was maintained at the end of 10 years, and the endurance level was at least 105 program/erase cycles. Over-erase, which was shown seriously in floating gate device, was not shown in SONOS device.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2007.05a
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• pp.473-477
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• 2007

The development of advanced Insulated Gate Bipolar Transistor(IGBT)has enabled high-frequency switching operation and has improved the performance of PWM inverters for motor drive. However, the high rate of dv/dt of IGBT has adverse effects on motor insulation stress. In many motor drive applications, the inverter and motor are separated and it requires long motor feds. The long cable contributes high frequency ringing at the motor terminal and it results in hight surge voltage which stresses the motor insulation. The inverter output filter and RDC snubber are conventional method which can reduce the surge voltage. In this paper, we propose the new low loss snubber to reduce the motor terminal surge voltage. The snubber consists of the series connection of charging/discharging capacitor and the voltage-clamped capacitor. At IGBT turn-off, the snubber starts to operate when the IGBT voltage reaches the voltage-clamped level. Since dv/dt is decreased by snubber operating, the peak level of the surge voltage can be reduced. Also the snubber operates at the IGBT voltage above the voltage-clamped level, the snubber loss is largely reduced comparing with RDC snubber. The proposed snubber enables to reduce the motor terminal surge voltage with low loss.