• JSTS:Journal of Semiconductor Technology and Science
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• 제8권2호
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• pp.111-114
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• 2008

We studied the influence of nanocrystalline silicon (nc-Si) thin film thickness on top gate nc-Si thin film transistor (TFT) fabricated at $180^{\circ}C$. The nc-Si thickness affects the characteristics of nc-Si TFT due to the nc-Si growth similar to a columnar. As the thickness of nc-Si increases from 40 nm to 200 nm, the grain size was increased from 20 nm to 40 nm. Having a large grain size, the thick nc-Si TFT surpasses the thin nc-Si TFT in terms of electrical characteristics such as field effect mobility. The channel resistance was decreased due to growth of the grain. We obtained the experimental results that the field effect mobility of the fabricated devices of which nc-Si thickness is 60, 90 and 130 nm are 26, 77 and $119\;cm^2/Vsec$, respectively. The leakage current, however, is increased from $7.2{\times}10^{-10}$ to $1.9{\times}10^{-8}\;A$ at $V_{GS}=-4.4\;V$ when the nc-Si thickness increases. It is originated from the decrease of the channel resistance.

• 한국재료학회지
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• 제15권5호
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• pp.301-305
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• 2005

We fabricated nickel silicide layers on whole non-patterned wafers from $p-Si(100)SiO_2(200nm)$/poly-Si(70 nm)mn(40 nm) structure by 40 sec rapid thermal annealing of $500\~900^{\circ}C$. The sheet resistance, cross-sectional microstructure, surface roughness, and phase analysis were investigated by a four point probe, a field emission scanning electron microscope, a scanning probe microscope, and an X-ray diffractometer, respectively. Sheet resistance was as small as $7\Omega/sq$. even at the elevated temperature of $900^{\circ}C$. The silicide thickness and surface roughness increased as silicidation temperature increased. We confirmed the nickel silicides iron thin nickel/poly-silicon structures would be a mixture of NiSi and $NiSi_2$ even at the $NiSi_2$ stable temperature region.

• 대한전자공학회논문지SD
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• 제37권12호
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• pp.1-9
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• 2000

미세구조 N-채널 MOSFET의 게이트-소스 전압에 의존하는 유효 채널 캐리어 이동도와 소스 및 드레인 기생저항의 정확한 분리 추출을 위해서 새로운 ERM-방법을 제안하였다. ERM-방법은 선형영역에서 동작하는 게이트 길이가 다른 두개의 소자($W_m/L_m=30{\mu}m/0.6{\mu}m, 30{\mu}m/1{mu}m$)에 적용되었고 유효 채널 캐리어 이동도를 모델링하고 추출하는 과정에서 게이트-소스 전압에 의존하는 소스 및 드레인 기생저항의 영향을 고려하였다. ERM-방법으로 추출된 특성변수들을 사용한 해석적 모델식과 소자의 측정데이터를 비교해본 결과 오차가 거의 없이 일치하는 것을 확인하였다. 따라서, ERM-방법을 사용하면 대칭구조 및 비대칭구조 소자의 유효 채널 캐리어 이동도, 소스 및 드레인 기생저항과 다른 특성변수들을 정확하고 효율적으로 추출할 수 있을 것으로 기대된다.

• 한국산학기술학회논문지
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• 제5권1호
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• pp.13-15
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• 2004

고속처리를 위한 나노급의 논리소자의 개발을 위해서는 소스/드레인 영역의 저항을 감소시키는 것이 필수적이다. 반도체소자의 개발 로드맵을 제시하고 있는 ITRS의 보고에 의하면 70㎚급 MOSFET에서는 채널영역의 저항에 대비하여 그 외의 영역이 나타내는 저항성분이 약 15% 이내로 제작되어야 할 것으로 예측하고 있다. 이 기준을 유지하기 위해서는 소스/드레인 영역의 각 전류 흐름에 기인하는 가상적 기생저항에 대한 성분 분리와 이들이 가지는 저항값에 대한 정량적 계산이 이루어져야 한다. 이에 본 논문은 calibration된 TCAD simulation을 통해 나노영역의 Tr.에서 저항성분을 계산, 평가하는 방법을 연구하였다. 특히, 소스/드레인 영역의 실리사이드 접촉 저항성분들을 최소화하여 optimize하기 위한 전략을 제시한다.

• 대한전자공학회논문지SD
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• 제45권9호
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• pp.21-25
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• 2008

본 연구에서는 MOSFET의 RF 성능을 극대화하기 위해 단위 게이트 finger 폭($W_u$)에 대한 $f_T$ 및 $f_{max}$의 종속데이터를 측정하고 이 결과를 소신호 모델 파라미터들을 추출함으로써 새롭게 분석하였다. 이러한 물리적 분석결과로 $f_T$의 최대값이 존재하는 원인은 좁은 $W_u$에서 $W_u$에 무관한 parasitic gate-bulk capacitance와 넓은 $W_u$에서 트랜스컨덕턴스의 증가율이 감소하는 wide width effect에 의한 것임을 알 수 있다. 또한, $f_{max}$의 최대값은 게이트저항이 좁은 $W_u$에서 크게 줄어들고 넓은 $W_u$에서 점점 일정하게 되는 non-quasi-static effect에 의해 발생된다는 사실이 밝혀졌다.

• 전자공학회논문지A
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• 제32A권6호
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• pp.82-90
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• 1995

We proposed SAW (Self-Algined Selectively Grown W-Gate) MOSFET structure, and strudied electrical characteristics of the fabricated SAW MOSFETs. The threshold volgate of 0.21${\mu}$m SAW NMOSFET was 0.18 V and that of 0.24 ${\mu}$m SAW PMOSFET was -0.16 V. The subthreshold slope was 74 mV/decade for NMOSFET and 82 mV/decade for PMOSFET. The maximum transconductance of NMOSFET and PMOSFET, at V$_{GS}$=2.5 V and V$_{DS}$=1.5 V, were260 mS/mm and 122 mS/mm. The measured saturation drain current at V$_{GS}$=V$_{DS}$ =2.5 V was 0.574 mA/${\mu}$m for NMOSFET and -0.228 mA/${\mu}$m for PMOSFET. The gate resistance of SAW MOSFET was about m$\Omega$cm and the n+-p junction capacitance of SAW MOSFET was about 10% lowas than that of the conventional MOSFET's.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권3호
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• pp.146-153
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• 2006

We have been investigating InGaAs HEMTs as a future high-speed and low-power logic technology for beyond CMOS applications. In this work, we have experimentally studied the role of the side-recess spacing $(L_{side})$ on the logic performance of 50 nm $In_{0.7}Ga_{0.3}As$ As HEMTs. We have found that $L_{side}$ has a large influence on the electrostatic integrity (or short channel effects), gate leakage current, gate-drain capacitance, and source and drain resistance of the device. For our device design, an optimum value of $L_{side}$ of 150 nm is found. 50 nm $In_{0.7}Ga_{0.3}As$ HEMTs with this value of $L_{side}$ exhibit $I_{ON}/I_{OFF}$ ratios in excess of $10^4$, subthreshold slopes smaller than 90 mV/dec, and logic gate delays of about 1.3 ps at a $V_{CC}$ of 0.5 V. In spite of the fact that these devices are not optimized for logic, these values are comparable to state-of-the-art MOSFETs with similar gate lengths. Our work confirms that in the landscape of alternatives for beyond CMOS technologies, InAs-rich InGaAs FETs hold considerable promise.

• 센서학회지
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• 제30권6호
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• pp.436-440
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• 2021

The impact of the gate length (L_g) on the DC and high-frequency characteristics of indium-rich In_0.8Ga_0.2As channel high-electron mobility transistors (HEMTs) on a 3-inch InP substrate was inverstigated. HEMTs with a source-to-drain spacing (L_SD) of 0.8 ㎛ with different values of L_g ranging from 1 ㎛ to 19 nm were fabricated, and their DC and RF responses were measured and analyzed in detail. In addition, a T-shaped gate with a gate stem height as high as 200 nm was utilized to minimize the parasitic gate capacitance during device fabrication. The threshold voltage (V_T) roll-off behavior against L_g was observed clearly, and the maximum transconductance (g_{m_max}) improved as L_g scaled down to 19 nm. In particular, the device with an L_g of 19 nm with an L_SD of 0.8 mm exhibited an excellent combination of DC and RF characteristics, such as a g_{m_max} of 2.5 mS/㎛, On resistance (R_ON) of 261 Ω·㎛, current-gain cutoff frequency (f_T) of 738 GHz, and maximum oscillation frequency (f_max) of 492 GHz. The results indicate that the reduction of L_g to 19 nm improves the DC and RF characteristics of InGaAs HEMTs, and a possible increase in the parasitic capacitance component, associated with T-shap, remains negligible in the device architecture.

• E2M - 전기 전자와 첨단 소재
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• 제8권5호
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• pp.626-632
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• 1995

In this paper, The effect of the impedances in SNOSFET's memory devices has been developed. The effect of source and drain impedances measured by means of two bias resistances - field effect bias resistance by inner region, external bias resistance. The effect of the impedances by source and drain resistance shows the dependence of the function of voltages applied to the gate. It shows the differences of change in source drain voltage by means of low conductance state and high conductance state. It shows the delay of threshold voltages. The delay time of low conductance state and high conductance state by the impedances effect shows 3[.mu.sec] and 1[.mu.sec] respectively.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 1997년도 추계학술발표회논문집
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• pp.11-13
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• 1997

Abstract - An electronic starter using MOSFET has been designed to take advantage of ideal preheating and starting features which can extend the lifetime of fluorescent lamps. The preheating circuit of the developed electronic starter is consisted of four parts - afull-wave rectifier circuit, an FET switching circuit a timer circuit for the gate switching, and a circuit for end-of-life protection. The circuit is analyzed by using PSpice simulation, and is improved to give an appropriate starting-time through control of R-C time constant of the timer circuit. And the circuit is also provided with an end-of-life protection feature, which utilizes the negative resistance characteristics of a thermistor that is thermally linked to FET through a heatsink. This also protects the FET from any overheating problems. From the results of simulation it is possible to obtain an appropriate value on the starting time for proper ignition and also it is verified that the limit for resistance of the thermistor is dependant on the value of resistance is the timer circuit