• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.6
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• pp.473-479
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• 2011

In this paper, we have compared amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) with the nano-crystalline embedded-IGZO ($N_c$-embedded-IGZO) TFT fabricated by solid-phase crystallization (SPC) technique. The field effect mobility (${\mu}_{FE}$) of $N_c$-embedded-IGZO TFT was 2.37 $cm^2/Vs$ and the subthreshold slope (S-factor) was 0.83 V/decade, which showed lower performance than those of a-IGZO TFT (${\mu}_{FE}$ of a-IGZO was 9.67 $cm^2/Vs$ and S-factor was 0.19 V/decade). This results originated from generation of oxygen vacancies in oxide semiconductor and interface between gate insulator and semiconductor due to high temperature annealing process. However, the threshold voltage shift (${\Delta}V_{TH}$) of $N_c$-embedded-IGZO TFT was 0.5 V, which showed 1 V less shift than that of a-IGZO TFT under constant current stress during $10^5$ s. This was because there were additionally less increase of interface trap charges in Nc-embedded-IGZO TFT than a-IGZO TFT.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.180-180
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• 2010

Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

• Journal of the Korean Institute of Telematics and Electronics
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• v.16 no.4
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• pp.36-46
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• 1979

Using N_ Ch silicon gate technology . the capacitors and transistors with various dimenssion were fabricated. Although the applied process was somewhat standard the conditions of ion implantation for the gate were varied by changing the implant energies from 30keV to 60keV for B and from 100 keV to 175keV for P . The doses of the implant also changed from 3 $\times$ 10 /$\textrm{cm}^2$ to 5 $\times$ 10 /$\textrm{cm}^2$ for B and from 4$\times$ 10 /$\textrm{cm}^2$ to 7 $\times$ 10 /$\textrm{cm}^2$ for P . The D. C. parameters such as threshold voltage. substrate doping level, the degree of inversion, capacitance. flat band voltage, depletion layer width, gate oxide thickless, surface states, motile charge density, electron mobility. leakage current were evaluated and also compared with the corresponing theoretical values and / or good numbers for application. The threshold voltages measured using curve tracer and C-V plot gave good agreements with the values calculated from SUPREM II which has been developed by Stanford University process group. The threshold vol tapes with back gate bias were used to calculate the change of the substrate doping level. The measured subthreshold slope enabled the prediction of the degree of inversion The D. C. testing results suggest the realized capacitors and transistors are suited for the memory applications.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1833-1835
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• 1999

게이트 산화막의 breakdown 전압을 나추기 위해 질소 주입을 하는 과정은 실리콘층에 패드 산화막을 성장시킨 후 실리콘과 패드 산화막 층사이에 질소 이온을 주입하였다. 이온 주입 후 패드 산화막 층을 제거하고 그 위에 게이트 산화막 층을 성장시키는 방법을 사용하였다. 이러한 방법을 질소 이온의 농도를 변화시키면서 여러번 반복하였다 그래서 질소 이온 농도의 변화에 따른 게이트 산화막 두께의 변화를 측정하였다. 그 결과 질소 농도이 따른 게이트 산화막 성장비율을 알아 보았다. 그리고 질소 농도의 변화에 따른 Breakdown 전압과 누설 전류의 변화를 측정하였다. 또한 앞에서 말한 질소 주입 공정이 들어가면서 추가적으로 발생하는 과정에 대해 고찰하였다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.4 no.4
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• pp.2-12
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• 1967

A pair of insulated-gate metal-oxide-semiconductor field-effect transistor has been used to measure the direct current produced from the ionization chamber in the range of to A. An analisis of direct-current differential amplifier giving the expressions of the common-mode rejection ratio and the rralization of the constant-current generator to give very large effective source resistance has been presented. Voltage gain is 6.6, drift at the room temperature is 1.5mv per day. The common-mode rejection ratio is obtained maximum 84db. These facts give the feasibility of small direct-current measurements by utilizing this type transistors.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.5
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• pp.270-277
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• 2000

A new Lateral Trench-MOS Bipolar-Mode Field-Effect Transistor(LTMBMFET) is proposed and verified by MEDICI simulation. By using a trench MOS structure, the proposed device can enhance the current gain without sacrificing other device characteristics such as the breakdown voltage. The channel region of the proposed device is formed between the trench MOS structure. So the effect of the substrate voltage is negligible when compared with the conventional device which has a channel region between the gate junction and the buried oxide layer.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.318-321
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• 2000

We showed that the change of Ar to $N_2$flow during the TiN deposition by the reactive sputtering decides the crystallinity of LPCVD W, as well as the electrical properties of the W-TiN/SiO$_2$Si capacitor. In particular, the threshold voltage can be controlled by the Ar to $N_2$ratio. As compared to the results obtained from the LPCVD W/SiO$_2$/Si MOS capacitor, the insertion of approximately 50 nm TiN film effectively prohibits the fluorine diffusion during the deposition and annealing of W films, resulting in negligible leakage currents at the low electric fields.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.579-582
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• 2005

In this study, the electrical characteristic of asymmetric high voltage MOSFET (AHVMOSFET) for display IC was investigated. Measurement data are taken over range of temperature (300K-400K) and various extended drain length, and gate oxide thickness ($175{\AA}$, $350{\AA}$). In high temperature condition, drain current decreased over 30% and max transconductance deceased over 40%, and specific on-resistance increased over 30% in comparison with room temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.97-98
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• 2009

Tunneling barrier engineered charge trap flash (TBE-CTF) memory capacitor were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectrics layers were used as engineered tunneling barrier. The charge trapping characteristic with different metal gates are also investigated. A larger memory window was achieved from the TBE-CTF memory with high workfunction metal gate.

• Journal of Sensor Science and Technology
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• v.26 no.2
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• pp.79-84
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• 2017

The drain current of the SB MOSFET was analytically modeled by an equation composed of thermionic emission and tunneling with consideration of the image force lowering. The depletion region electron concentration was used to model the channel electron concentration for the tunneling current. The Schottky barrier width is dependent on the channel electron concentration. The drain current is changed by the gate oxide thickness and Schottky barrier height, but it is hardly changed by the doping concentration. For a GaN SB MOSFET with ITO source and drain electrodes, the calculated threshold voltage was 3.5 V which was similar to the measured value of 3.75 V and the calculated drain current was 1.2 times higher than the measured.