• 한국정보통신학회논문지
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• 제7권4호
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• pp.719-724
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• 2003

본 논문은 halo doping profile을 갖는 나노구조 LDD MOSFET의 문턱전압에 대하여 연구하였다. 소자의 크기는 일반화된 스켈링 이론을 사용하여 100nm 에서 40m까지 스켈링하였다. Van Dort Quantum Correction Model(QM) 모델을 정전계 스켈링 이론과 정전압 스켈링 이론에 적용하여 문턱전압을 조사하였으며, gate oxide 두께의 변화 따른 direct tunneling current를 조사하였다. 결과적으로 게이트 길이가 감소됨에 따라 문턱전압이 정전계 스켈링에서는 감소하고 정전압 스켈링에서는 증가함을 알았고 direct tunneling current는 gate oxide 두께가 감소함에 따라 증가됨을 알았다. 또한 채널 길이의 감소에 따른 MOSFET의 문턱전압에 대한 roll-off특성을 최소화하기 위하여 일반화된 스켈링에서 $\alpha$값은 거의 1 이여야 함을 알았다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.653-653
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• 2013

In this study, ITO extended gate reduced graphene oxide field effect transistor (rGO FET) was demonstrated as a transducer for a proton sensing application. In this structure, the sensing area is isolated from the active area of the device. Therefore, it is easy to deposit or modify the sensing area without affecting on the device performance. In this case, the ITO extended gate was used as a gate electrode as well as a proton sensing material. The proton sensing properties based on the rGO FET transducer were analyzed. The rGO FET device showed a high stability in the air ambient with a TTC encapsulation layer for months. The device showed an ambipolar characteristic with the Dirac point shift with varying the pH solutions. The sensing characteristics have offered the potential for the ion sensing application.

• 전자공학회논문지D
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• 제35D권7호
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• pp.79-87
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• 1998

Nitrided oxides which have been investigated as alternative gate oxide for metal-oxide-semiconductor field effect devices were grown by two-step process using N$_{2}$O gas, and were chaacterized via a fowler-nordheim tunneling(FNT) electron injection technique. Electrical characteristics of nitrided gate oxides were superior to that of control oxides.Further, the FNT electron injection into the nitrided gate oxides reveals that gate oxides degrade more both if electrons were foreced to inject from the gate metal and if thicker nitrided gate oxides were used in the thickness range of 90~130.angs.. Models are suggested to explain these phenomena.

• 한국전기전자재료학회논문지
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• 제37권5호
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• pp.507-511
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• 2024

Various process modifications have been used to minimize SiO₂ gate oxide aging in metal-oxide-semiconductor field-effect transistors (MOSFETs). In particular, post-metallization annealing (PMA) with a deuterium ambient can effectively eliminate both bulk traps and interface traps in the gate oxide. However, even with the use of PMA, it remains difficult to prevent high levels of radiation-induced gate oxide damage such as total ionizing dose (TID) during long-term missions. In this context, additional low-temperature heat treatment (LTHT) is proposed to recover from radiation-induced damage. Positive traps in the damaged gate oxide can be neutralized using LTHT, thereby prolonging device reliability in harsh radioactive environments.

• 센서학회지
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• 제28권2호
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• pp.76-80
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• 2019

The characteristics of a titanium oxide layer prepared using a plasma electrolytic oxidation (PEO) process were investigated, using an extended gate ion sensitive field effect transistor (EG-ISFET) to confirm the layer's capability to react with hydrogen ions. The surface morphology and element distribution of the PEO-processed titanium oxide were observed and analyzed using field-emission scanning-electron microscopy (FE-SEM) and energy-distribution spectroscopy (EDS). The titanium oxide prepared by the PEO process was utilized as a hydrogen-ion sensing membrane and an extended gate insulator. A commercially available n-channel enhancement MOS-FET (metal-oxide-semiconductor FET) played a role as a transducer. The responses of the PEO-processed titanium oxide to different pH solutions were analyzed. The output drain current was linearly related to the pH solutions in the range of pH 4 to pH 12. It was confirmed that the titanium-oxide layer prepared by the PEO process could feasibly be used as a hydrogen-ion-sensing membrane for EGFET measurements.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.130-131
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• 2005

In the era of submicron devices, super ultra thin gate oxide characteristics are required. Titanium silicide process has studied gate oxide reliability and dielectric strength characteristics as the composition of gate electrode. In this study the author observed process characteristics on MOS structure. In view point of the process characteristics of MOS capacitor, the oxygen & Ti, Si2 was analyzed by SIMS analysis on before and after annealing with 1,2 step silicidation, the Ti contents[Count/sec]of $9.5{\times}1018$ & $6.5{\times}1018$ on before and after 2'nd anneal. The oxygen contents[Count/sec] of $4.3{\times}104$ & $3.65{\times}104$, the Si contents[Count/sec] of $4.2{\times}104$ & $3.7{\times}104$ on before and after 2'nd anneal. The rms value[A] was 4.98, & 4.03 on before and after 2'nd anneal.

• 한국전기전자재료학회논문지
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• 제16권3호
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• pp.181-185
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• 2003

Influence of post gate oxidation anneal on Negative Bias Temperature Instability (NBTI) of PMOSFE has been investigated. At oxidation anneal temperature raised above 950$^{\circ}$C, a significant improvement of NBTI was observed which enables to reduce PMO V$\_$th/ shift occurred during a Bias Temperature (BT) stress. The high temperature anneal appears to suppress charge generations inside the gate oxide and near the silicon oxide interface during the BT stress. By measuring band-to-band tunneling currents and subthreshold slopes, reduction of oxide trapped charges and interface states at the high temperature oxidation anneal was confirmed.

• 한국전기전자재료학회논문지
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• 제16권9호
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• pp.765-770
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• 2003

We have developed a low-temperature, and low-pressure radical induced oxidation (RIO) technology, so that high-quality ultrathin silicon dioxide layers have been effectively produced with a high reproducibility, and successfully employed to realize high performace SiGe heterostructure complementary MOSFETs (HCMOS) lot the first time. The obtained oxide layer showed comparable leakage and breakdown properties to conventional furnace gate oxides, and no hysteresis was observed during high-frequency capacitance-voltage characterization. Strained SiGe HCMOS transistors with a 2.5 nm-thick gate oxide layer grown by this method exhibited excellent device properties. These suggest that the present technique is particularly suitable for HCMOS devices requiring a fast and high-precision gate oxidation process with a low thermal budget.

• Journal of Electrical Engineering and information Science
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• 제3권2호
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• pp.261-266
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• 1998

This paper describes the fabrication and characterization of dual-polysilicon gated surface channel 0.1$\mu\textrm{m}$ CMOSFETs using BF2 and arsenic as channel dopants. We have used and LDD structure and 40${\AA}$ gate oxide as an insulator. To suppress short channel effects down to 0.1$\mu\textrm{m}$ channel length, shallow source/drain extensions implemented by low energy implantation and SSR(Super Steep Retrograde) channel structure were used. The threshold voltages of fabricated CMOSFETs are 0.6V. The maximum transconductance of nMOSFET is 315${\mu}$S/$\mu\textrm{m}$, and that of pMOSFET is 156 ${\mu}$S/$\mu\textrm{m}$. The drain saturation current of 418 ${\mu}$A/$\mu\textrm{m}$, 187${\mu}$A/$\mu\textrm{m}$ are obtained. Subthreshold swing is 85mV/dec and 88mV/dec, respectively. DIBL(Drain Induced Barrier Lowering) is below 100mV. In the device with 2000${\AA}$ thick gate polysilicon, depletion in polysilicon near the gate oxide results in an increase of equivalent gate oxide thickness and degradation of device characteristics. The gate delay time is measured to be 336psec at operation voltage of 2V.

• 한국전기전자재료학회논문지
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• 제17권7호
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• pp.713-717
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• 2004

In this study, the etched trench properties including cross-sectional profile, surface roughness, and crystalline defects were investigated depending on the various silicon etching and additive gases, For the case of HBr$He-O_2SiF_4$ trench etching gas mixtures, the excellent trench profile and minimum defects in the silicon trench were achieved. Due to the residual oxide film grown by the additive oxygen gas, which acts as a protective layer during trench etching, the undercut and defects generation in the trench were suppressed. To improve the electrical characteristics of trench gate, the hydrogen annealing process after trench etching was also adopted. Through the hydrogen annealing, the trench corners might be rounded by the silicon atomic migration at the trench corners having high potential. The rounded trench corner can afford to reduce the gate electric field and grow a uniform gate oxide. As a result, dielectric strength and TDDB characteristics of the hydrogen annealed trench gate oxide were remarkably increased compared to the non-hydrogen annealed one.