• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.4
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• pp.271-274
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• 2013

Power Metal Oxide Semiconductor Field Effect Transistor's (MOSFETs) are well known for superior switching speed, and they require very little gate drive power because of the insulated gate. In these respects, power MOSFETs approach the characteristics of an "ideal switch". The main drawback is on-resistance RDS(on) and its strong positive temperature coefficient. While this process has been driven by market place competition with operating parameters determined by products, manufacturing technology innovations that have not necessarily followed such a consistent path have enabled it. This treatise briefly examines metal oxide semiconductor (MOS) device characteristics and elucidates important future issues which semiconductor technologists face as they attempt to continue the rate of progress to the identified terminus of the technology shrink path in about 2020. We could find at the electrical property as variation p base dose. Ultimately, its ON state voltage drop was enhanced also shrink chip size. To obtain an optimized parameter and design, we have simulated over 500 V Field ring using 8 Field rings. Field ring width was $3{\mu}m$ and P base dose was $1e15cm^2$. Also the numerical multiple $2.52cm^2$ was obtained which indicates the doping limit of the original device. We have simulated diffusion condition was split from $1,150^{\circ}C$ to $1,200^{\circ}C$. And then $1,150^{\circ}C$ diffusion time was best condition for break down voltage.

• Korean Journal of Materials Research
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• v.9 no.11
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• pp.1117-1122
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• 1999

Amorphous Si and Co/Ti bilayers were sequentially evaporated onto 5- 10nm thick $\textrm{CoSi}_{2}$ and rapidly thermal-annealed(RTA) to form Co-polycide electrodes. Then, MOS capacitors were fabricated by doping poly-Si using SADS method. The C-V and leakage-current characteristics of the capacitors depending upon the RTA conditions were measured to study the effects of thermal stability of $\textrm{CoSi}_{2}$ and dopant redistribution on electrical properties of Co -polycide gates. Capacitors RTAed at $700^{\circ}C$ for 60-80 sec., showed excellent C-V and leakage-current characteristics due to degenate doping of poly-Si layers. But for longer time or at higher temperature, their electrical properties were degraeded due to $\textrm{CoSi}_{2}$ decomposition and subsequent Co diffusion. When making Co-polycide gate electrodes by SADS, not only degenerate doping of poly-Si layer. but also suppression of have been shown to be very critical.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.431-433
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• 2009

We developed 4.8 inch WQVGA e-paper on plastic substrate using organic field effect transistors (OFETs). Polyethylene naphthalate (PEN) film was used as a flexible substrate and arrays of OFETs with bottom-gate, bottom-contact structure were fabricated on it. Lowtemperature curable organic gate insulating materials were employed and polymer semiconductor solutions were ink-jetted on arrays with high-resolution. At all steps, process temperature was limited below $130^{\circ}C$. Finally, we could drive flexible e-paper displays based on OFET arrays with the resolution of 100 dpi.

• Journal of Convergence for Information Technology
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• v.11 no.7
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• pp.104-110
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• 2021

A novel selective oxidation process has been developed for low source/drain (S/D) series resistance of the fin channel metal oxide semiconductor field effect transistor (MOSFET). Using this technique, the selective oxidation fin-channel MOSFET (SoxFET) has the gate-all-around structure and gradually enhanced S/D extension regions. The SoxFET demonstrated over 70% reduction in S/D series resistance compared to the control device. Moreover, it was found that the SoxFET behaved better in performance, not only a higher drive current but also higher transconductances with suppressing subthreshold swing and drain induced barrier lowering (DIBL) characteristics, than the control device. The saturation current, threshold voltage, peak linear transconductance, peak saturation transconductance, subthreshold swing, and DIBL for the fabricated SoxFET are 305 ㎂/㎛, 0.33 V, 13.5 𝜇S, 76.4 𝜇S, 78 mV/dec, and 62 mV/V, respectively.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2007.05a
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• pp.473-477
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• 2007

The development of advanced Insulated Gate Bipolar Transistor(IGBT)has enabled high-frequency switching operation and has improved the performance of PWM inverters for motor drive. However, the high rate of dv/dt of IGBT has adverse effects on motor insulation stress. In many motor drive applications, the inverter and motor are separated and it requires long motor feds. The long cable contributes high frequency ringing at the motor terminal and it results in hight surge voltage which stresses the motor insulation. The inverter output filter and RDC snubber are conventional method which can reduce the surge voltage. In this paper, we propose the new low loss snubber to reduce the motor terminal surge voltage. The snubber consists of the series connection of charging/discharging capacitor and the voltage-clamped capacitor. At IGBT turn-off, the snubber starts to operate when the IGBT voltage reaches the voltage-clamped level. Since dv/dt is decreased by snubber operating, the peak level of the surge voltage can be reduced. Also the snubber operates at the IGBT voltage above the voltage-clamped level, the snubber loss is largely reduced comparing with RDC snubber. The proposed snubber enables to reduce the motor terminal surge voltage with low loss.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.421-427
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• 2009

We successfully fabricated 4.7-inch organic thin film transistors array with $640{\times}480$ pixels on flexible substrate. All the processes were done by photolithography, spin coating and ink-jet printing. The OTFT-Electrophoretic (EP) pixel structure, based on a top gate OTFT, was fabricated. The mobility, ON/OFF ratio, subthreshold swing and threshold voltage of OTFT on flexible substrate are: 0.01 ^2/V-s, 1.3 V/dec, 10E5 and -3.5 V. After laminated the EP media on OTFT array, a panel of 4.7-inch $640{\times}480$ OTFT-EPD was fabricated. All of process temperature in OTFT-EPD is lower than $150^{\circ}C$. The pixel size in our panel is $150{\mu}m{\times}150{\mu}m$, and the aperture ratio is 50 %. The OTFT channel length and width is 20 um and 200um, respectively. We also used OTFT to drive EP media successfully. The operation voltages that are used on the gate bias are -30 V during the row data selection and the gate bias are 0 V during the row data hold time. The data voltages that are used on the source bias are -20 V, 0 V, and 20 V during display media operation.

• Journal of Advanced Navigation Technology
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• v.10 no.2
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• pp.167-172
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• 2006

In this paper, the 25W power amplifier for UHF band radio transceiver has been designed and realized. The power amplifier was composed of drive, power amplifier and control stages. Feedback topology and coaxial line baluns were used for wide band operation. The VDMOS, which has reliable performance for linearity and efficiency, was used for power device and designed to operate as push-pull amplification at Class AB Bias. The power amplifier designed in such a way was found to show stable AM modulation performance when voice signal was detected at the gate stage, with being designed and realized to meet output specifications of commercial air traffic control transmitter.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.9
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• pp.124-129
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• 2009

Recently, PWM inverter is widely utilized for many industrial applications such as high performance drive and space vector pulse width modulation(SVPWM) inverter which has high voltage ratio and low harmonics compared to conventional PWM inverter. This paper presents the implementation on a field programmable gate array(FPGA) of a SVPWM module for a voltage source inverter. The SVPWM module consists of PWM generator, current and position sensor interface and dead time compensator. The implemented SVPWM module can be integrated with a digital signal processor(DSP) to provide a flexible and effective solution for high performance voltage source inverter and for the use of multi-motor control. The performance of SVPWM module is verified by simulation and several experimental results.

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.430-433
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• 2003

IGBTS are widely used for the industrial inverters in the mid power range at low voltage (440V$\~$660V) application. Advantageous features of the device are simple gate drive and high speed switching capability. Due to these advantages the application of IGBTS is enlarging into the high power application. However, to increase the power handling capacity at lower input voltage level, the current rating in each bridge arm must be enlarged. Therefore the parallel operation of IGBT devices is essentially needed. This paper describes the feasible parallel structures of the power circuit for the mid & the high power inverters and introduces the important design condition for the parallel operation of IGBT devices. To verify feasibility of the IGBT parallel operation, the feature of several IGBT devices (EUPEC, SEMIKRON's IGBT) are investigated and the power stacks are implemented and tested with these devices. The experimental results show the good characteristics for the parallel operation of IGBTS.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.11
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• pp.910-917
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• 2009

We have designed a new structures of Junction Field Effect Transistor(JFET) using SILVACO simulation to improve electrical properties and process reliability. The device structure and process conditions of Si control JFET(Si JFET) were determined to set cut off voltage and drain current(at Vg=0 V) to -0.46 V and $300\;{\mu}A$, respectively. Among many design parameters influencing the performance of the device, the drive-in time of p-type gate is presented most predominant effects. Therefore we newly designed SiGe JFET, in which SiGe layers were placed above and underneath of Si-channel. The presence of SiGe layer could lessen Boron into the n-type Si channel, so that it would be able to enhance the structural consistency of p-n-p junction. The influence of SiGe layer could be explained in conjunction with boron diffusion and corresponding I-V characteristics in comparison with Si-control JFET.