• ETRI Journal
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• v.36 no.1
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• pp.89-98
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• 2014

The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube field-effect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.232-235
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• 1999

In this paper, we present a coprocessor that can operate with ARM microprocessors. The coprocessor supports IEEE 754 standard single- and double-precision binary floating point arithmetic operations. The design objective is to achieve minimum-area, low-power and acceleration of processing power of ARM microprocessors. The instruction set is compatible with ARM7500FE. The coprocessor is written in verilog HDL and synthesized by the SYNOPSYS Design Compiler. The gate count is 38,115 and critical path delay is 9.52ns.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.153-160
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• 2004

In this paper, we propose an efficient bit loading algorithm for IEEE 802.11a wireless LAN systems. While a conventional bit loading algorithm uses the SNR value of each subcarrier, it is very difficult to estimate the exact SNR value in wireless LAN systems due to randomness of AWGN. Therefore, in order to solve this problem our proposed algorithm uses the channel frequency response instead of the SNR of each subcarrier. Through simulation results, we can obtain the performance gain of 3.5∼8㏈ at PER of 10-2 with the proposed bit loading algorithm while the conventional one obtains the performance gain of 0.5∼5㏈ at the same conditions. Also, the increased data rate can be confirmed 63Mbps. After the logic synthesis using 0.3${\mu}{\textrm}{m}$ CMOS technology, the logic gate count for the processor with proposed algorithm can be reduced by 34% in comparison with the conventional one.

• Journal of IKEEE
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• v.18 no.1
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• pp.165-171
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• 2014

This paper presents a low complexity QR decomposition (QRD) architecture for MIMO detector. In the proposed approach, various CORDIC-based QRD algorithms are efficiently combined together to reduce the computational complexity of the QRD hardware. Based on the computational complexity analysis on various QRD algorithms, a low complexity approach is selected at each stage of QRD process. The proposed QRD architecture can be applied to any arbitrary dimension of channel matrix, and the complexity reduction grows with the increasing matrix dimension. Our QR decomposition hardware was implemented using Samsung $0.13{\mu}m$ technology. The numerical results show that the proposed architecture achieves 47% increase in the QAR (QRD Rate/Gate count) with 28.1% power savings over the conventional Householder CORDIC-based architecture for the $4{\times}4$ matrix decomposition.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.48-57
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• 2003

In this paper, An 8${\times}$l ID-IDCT processor with adder-based distributed arithmetic(DA) and bit-serial method Is presented. To reduce hardware cost and to improve operating speed, the proposed 8${\times}$1 ID-IDCT used the bit-serial method and DA method. The transform of coefficient equation results in reduction in hardware cost and has a regularity in implementation. The sign extension computation method reduces operation clock. As a result of logic synthesis, The gate count of designed 8${\times}$1 1D-IDCT is 17,504. The sign extension processing block has gate count of 3,620. That is 20% of total 8${\times}$1 ID-IDCT architecture. But the sign extension processing block improves more than twice in throughput. The designed IDCT processes 50Mpixels per second and at a clock frequency of 100MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.5
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• pp.857-864
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• 2006

This paper describes a design of low-power/small-area arithmetic circuits which are vector processing unit powering nit, divider unit and square-root unit for mobile 3D graphic accelerator. To achieve area-efficient and low-power implementation that is an essential consideration for mobile environment, the fixed-point f[mat of 16.16 is adopted instead of conventional floating-point format. The vector processing unit is designed using redundant binary(RB) arithmetic. As a result, it can operate 30% faster and obtained gate count reduction of 10%, compared to the conventional methods which consist of four multipliers and three adders. The powering nit, divider unit and square-root nit are based on logarithm number system. The binary-to-logarithm converter is designed using combinational logic based on six-region approximation method. So, the powering mit, divider unit and square-root unit reduce gate count when compared with lookup table implementation.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.3
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• pp.201-207
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• 2008

This paper presents the implementation of a Tiling System about Preprocessing functions of JPEG 2000. The system covers the JPEG 2000 standard and is designed to determine the size of the image, to expand the image area and to split input image into several tiles. In order to split the input image with the progressive transmission into several tiles and transmit a tile of this image to others, this system store this image into Frame Memory. Therefore, this is designed as the Finite State Machine (FSM) to sequence through specific patterns of states in a predetermined sequential manner by using Verilog-HDL and be designed to handle a maximum 5M image. Moreover, for identifying image size for expansion, we propose several formula which are based on remainder after division (rem). we propose the true table which determines the size of the image input patterns by using results of these formula. Under the condition of TSMC 0.25um ASIC library, gate count is 18,725 and maximum data arrival time is 18.94 [ns].

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.10A
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• pp.809-815
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• 2011

In this paper, we have proposed and implemented a novel architecture which can be used to effectively design the modified Euclidean (ME) algorithm for key equation solver (KES) block in high-speed Reed-Solomon (RS) decoder. With polynomial expressions of newly-defined state variables for controlling each processing element (PE), the proposed architecture has simple input/output signals and requires less hardware complexity because no degree computation circuits are needed. In addition, since each PE circuit is independent of the error correcting capability t of RS codes, it has the advantage of linearly increase of the hardware complexity of KES block as t increases. For comparisons, KES block for RS(255,239,8) decoder is implemented using Verilog HDL and synthesized with 0.13um CMOS cell library. From the results, we can see that the proposed architecture can be used for a high-speed RS decoder with less gate count.

• Journal of Broadcast Engineering
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• v.16 no.1
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• pp.174-177
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• 2011

In this paper, we investigate a method for designing FIR filters with CSD coefficients. Firstly, the H/W complexity of a CSD FIR filter is estimated in terms of number of gates. Using the estimated complexity, an optimal filter that can meet the required performance with minimal H/W complexity can be designed. Next, based on the MILP problem solver called BonsaiG, we present a filter design program. From the two design examples, it is demonstrated that an optimal filter can be obtained by comparing the complexity of the candidate filters in terms of the gate counts, whose differences are estimated to be about 400-600 gates.

• Proceedings of the KSR Conference
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• 2009.05a
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• pp.247-250
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• 2009

Awareness of resource conservation and pollution prevention has been continually increasing. The proven benefits from CFRP's unique combination of light weight and high strength compare to conventional material is well suited for minimizing fuel consumption during vehicle in particular rail operation. Responding the awareness, this work intends to study CFRP's recycling method that is not only technical performance but also environmental view point. According to prior work of technical performance test, this work aims at quantifying the footprint of energy and GHG derived from the two appreciated performance of pyrolysis and acids recycling methods. The streamline LCA is the concept for systematic assessment. The boundary is scoped at the recycling activity, consequently, the data in and out from the specific target activity are obtained under the gate to gate data collection. Its function is recovery carbon fiber. To count and compare function, functional unit is set at 60% of recycling rate. Korea database is mainly source for acquiring the footprint of both. The numerical results presented that the energy footprint of acids and pyrolysis is 164.95 and 1,199.88 MJ-eq., respectively. Meantime, the GHG footprint of is 1,196.22 and 5,916.08 g CO2 eq. for acids and pyrolysis. In summary, the acids recycling method is, in regarding the environmental performance, better than pyrolysis recycling method.