1 |
Hanho Lee, "High-Speed VLSI Architecture for Parallel Reed-Solomon Decoder," IEEE Trans. on VLSI Systems, Vol.11, No.2, pp.288-294, April 2003.
DOI
ScienceOn
|
2 |
S. Lee, H. Lee, "A High-Speed Pipelined Degree- Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders," IEICE Trans. Fundamentals, Vol.E91-A, No.3, pp.830-835, March, 2008.
DOI
ScienceOn
|
3 |
J. H. Baek and M. H. SunWoo, "New degree computationless modified Euclid's algorithm and architecture for Reed-Solomon decoder", IEEE Trans. Very Large Integr. (VLSI) Syst., Vol.14, No.8, pp.915-920, Aug. 2006.
DOI
ScienceOn
|
4 |
J. H. Baek and M. H. SunWoo, "Enhanced degree computationless modified Euclid's algorithm for Reed-Solomon decoders," Electronics Letters, Vol.43, No.3, pp.175-176, Feb., 2007.
DOI
ScienceOn
|
5 |
강성진, 김한종 "UWB 시스템을 위한 RS(23,17) 복호기 최적 설계," 한국통신학회논문지, Vol.33, No.8, pp.821-828, Aug., 2008.
|
6 |
J. Proakis, M. Salehi, Digital Communications, McGraw-Hill, 5th ed., 2008
|
7 |
L. Song, M. Yu, M. Shaffer, "10- and 40-Gb/s Forward Error Correction Devices for Optical Communications," IEEE Journal of Soild-State Circuits, Vol.37, No.11, pp.1565-1573, Nov. 2002.
DOI
ScienceOn
|
8 |
S. B. Wicker, Error Control Systems for Digital Communication and Storage, Englewood Cliffs, NJ, Prentice-Hall, 1995.
|
9 |
H. Shao, T. Truong, L. Deutsch, J. Yuen, I. Reed, "A VLSI design of a Pipeline Reed-Solomon Decoder," IEEE Trans. on Computers, Vol.c-34, No.5, pp.393-403, May 1985.
DOI
ScienceOn
|