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A Design of high throughput IDCT processor in Distrited Arithmetic Method  

김병민 (라이온텍)
배현덕 (충북대학교 전자공학과)
조태원 (충북대학교 전자공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.40, no.6, 2003 , pp. 48-57 More about this Journal
Abstract
In this paper, An 8${\times}$l ID-IDCT processor with adder-based distributed arithmetic(DA) and bit-serial method Is presented. To reduce hardware cost and to improve operating speed, the proposed 8${\times}$1 ID-IDCT used the bit-serial method and DA method. The transform of coefficient equation results in reduction in hardware cost and has a regularity in implementation. The sign extension computation method reduces operation clock. As a result of logic synthesis, The gate count of designed 8${\times}$1 1D-IDCT is 17,504. The sign extension processing block has gate count of 3,620. That is 20% of total 8${\times}$1 ID-IDCT architecture. But the sign extension processing block improves more than twice in throughput. The designed IDCT processes 50Mpixels per second and at a clock frequency of 100MHz.
Keywords
DCT-IDCT;
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Times Cited By KSCI : 1  (Citation Analysis)
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