• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1577-1580
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• 1987

This paper proposes a gate and functional level logic simulator which can be run on XENIX O.S. The simulator has hierarchical structure including Hardware Description Language compiler, Waveform Description Language compiler, and Simulation Command Language compiler. The Hardware Description Language compiler generates data structure composed of gate structure, wire structure, condition structure, and event structure. Simulation algorithm is composed of selective trace and event-driven methods. To improve simulation speed, Cross Referenced Linked List Structure ia defined in building the data structure of circuits.

• Proceedings of the Korean Society of Agricultural Engineers Conference
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• 2003.10a
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• pp.227-230
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• 2003

The results of the field tests with the prototype of the improved screw type show that the opening torque was $5N{\cdot}m$, 64% decreased compared to $14N{\cdot}m$ of the existed diversion gates. Moreover, there were no any rust as well as physical changes with various weather condition. While the operating times of the conventional screw and worm gear typed diversion gates were 233sec and 495sec, respectively, the operating time of the improved screw type was only 32sec, only 13.7% and 6.5%, respectively, of them. The amount of leakage was 0.4 liter per minute for the improved screw typed diversion gate while the conventional gate was shown 1.5liter per minute according to gap, corrosion, defect, etc.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.13-16
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• 2002

In this study, the electrical characteristics of 100v-Class LDMOSFET for high temperature applicat -ions such as electronic control systems of automo -biles and motor driver were investigated. Measurement data are taken over wide range of temperature(300k-SOOK) and various gate length(1.5 #m-3.0#m, step 0.3). In high temperature condition(>500k), drain current decreased over 30%, and specific on- resistance increased about three times in comparison with room temperature. Moreover, the ratio ROJBV, a figure of merit of the device, increased with increasing temperature.

• Journal of Korean Society of Water and Wastewater
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• v.25 no.3
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• pp.349-357
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• 2011

This study has an objective to estimate effect on water-quality enhancement by removal of contaminated river-bed material using a two-dimensional numerical modeling in the Seonakdong River, the Pyunggang River and the Maekdo River. RMA2 and RMA4 models were used for flow and contaminant transport simulation, respectively. After the analysis of the effects of flow restoration plan for the Seonakdong River system made by Lee et al (2008), simulation have been performed about scenarios which contains operations of the Daejeo Gate, the Noksan Gate, the Makdo Gate (on planning), and the Noksan Pumping Station. Because there is no option for elution from bed sediment in the RMA4 model, a simple technique has been used for initial condition modification for elution. The analyses revealed that the effect on water quality improvement due to dredging of bed sediment seemed to be less than 10 % of the total effect. The most efficient measure for the water quality improvement of the river system was the linked operation of water-gates and pumping station.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2005.05a
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• pp.252-257
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• 2005

Injection molding is a very important industrial process for the manufacturing of plastics objects. During an injection molding process of composites, the fiber-matrix separation and fiber orientation are caused by the flow of molten polymer/fiber mixture. As a result, the product tends to be nonhomogeneous and anisotropic. Hence, it is very important to clarify the relations between separation' orientation and injection molding conditions. So far, there is no research on the measurement of fiber orientation using image processing. In this study, the effects of fiber content ratio and molding condition on the fiber orientation-angle distributions are studied experimentally. Using the image processing method, the fiber orientation distribution of weld-line in injection-molded products is assessed. And the effects of fiber content and injection mold-gate conditions on the fiber orientation are also discussed.

• Journal of Information Display
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• v.6 no.2
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• pp.16-18
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• 2005

Hybrid insulator pentacene thin film transistors (TFTs) are fabricated with thermally grown oxide and cross-linked polyvinylalcohol (PVA) including surface treatment by dilute ploymethylmethacrylate (PMMA) layer on $n^+$ doped silicon wafer. Through the optimization of $SiO_2$ layer thickness in hybrid insulator structure, carrier mobility is increased to more than 35 times than that of the TFT which has only a gate insulator of $SiO_2$ at the same electric field. The carrier mobility of $1.80cm^2$/V-s, subthreshold swing of 1.81 V/decade, and $I_{on}/I_{off}$ current ratio> $1.10{\times}10^5$ are obtained less than -30 V bias condition. The result is one of the best reported performances of pentacene TFTs with hybrid insulator including cross-linked PVA layer as a gate insulator at relatively low voltage operation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.12
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• pp.1069-1074
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• 2005

In this work, nano-needle structures ate formed to solve problem, related to low density of quantum dots for nano floating gate memory. Such structures ate fabricated and electrical properties' of MIS devices fabricated on the nano-structures are studied. Nano floating gate memory based on quantum dot technologies Is a promising candidate for future non-volatile memory devices. Nano-structure is fabricated by reactive ion etching using $SF_6$ and $O_2$ gases in parallel RF plasma reactor. Surface morphology was investigated after etching using scanning electron microscopy Uniform and packed deep nano-needle structure is established under optimized condition. Photoluminescence and capacitance-voltage characteristics were measured in $Al/SiO_2/Si$ with nano-needle structure of silicon. we have demonstrated that the nano-needle structure can be applicable to non-volatile memory device with increased charge storage capacity over planar structures.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.354-357
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• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.4
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• pp.247-252
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• 2012

IGBT (insulated gate bipolar transistor) has been widely used around the power industry as it has good switching performance and its excellent conductance. In order to reduce power loss during switch turn-on state, it is essential to reduce its resistance. However, trade off relationship between breakdown voltage and device conductance is the greatest obstacle on the way of improvement. Floating island structure is one of the solutions. Still, under optimized device condition for the best performance, improvement rate is negligible. Therefore, this paper suggests adding trench gate on floating island structure to eliminate JFET (junction field effect transistor) area to reduce resistance and activate floating island effect. Experimental result by 2D simulation using TCAD, shows 20% improvement of turn-on state voltage drop.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.35 no.4
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• pp.179-185
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• 2012

When manufacturing die casting mold, generally, the casting layout design should be considered based on the relation among injection system, casting condition, gate system, and cooling system. Also, the extent or the location of product defects was differentiated according to the various relations of the above conditions. In this research, in order to optimize casting design of an automobile part (Gear Box) Computer Aided Engineering (CAE) was performed by using the simulation software (Z Cast). The simulation results were analyzed and compared with experimental results. During the mold filling, internal porosities caused by air entrap were predicted and reduced remarkably by the modification of the gate system and the configuration of overflow. With the solidification analysis, internal porosities caused by the solidification shrinkage were predicted and reduced by the modification of the gate system. For making a better production die casting tool, cooling systems on several thick areas are proposed in order to reduce internal porosities caused by the solidification shrinkage.