• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.18 no.11
• /
• pp.996-1000
• /
• 2005

Experimental results are presented for the degradation of 3 nm-thick gate oxide $(SiO_2)$ under both Negative-bias Temperature Instability (NBTI) and Hot-carrier-induced (HCI) stresses using P and NMOSFETS, The devices are annealed with hydrogen or deuterium gas at high-pressure $(1\~5\;atm.)$ to introduce higher concentration in the gate oxide. Both interface trap and oxide bulk trap are found to dominate the reliability of gate oxide during electrical stress. The degradation mechanism depends on the condition of electrical stress that could change the location of damage area in the gate oxide. It was found the trap generation in the gate oxide film is mainly related to the breakage of Si-H bonds in the interface or the bulk area. We suggest that deuterium bonds in $SiO_2$ film are effective in suppressing the generation of traps related to the energetic hot carriers.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.5 no.3
• /
• pp.195-203
• /
• 2005

Recently, a novel multi-bit nonvolatile memory based on double gate (DG) MOSFET is proposed to overcome the short channel effects and to increase the memory density. We need more complex voltage schemes for DG MOSFET devices. In view of peripheral circuits driving memory cells, one should consider various voltage sources used for several operations. It is one of the key issues to minimize the number of voltage sources. This criterion needs more caution in considering a DG nonvolatile memory cell that inevitably requires more number of events for voltage sources. Therefore figuring out the permissible range of operating bias should be preceded for reliable operation. We found that reliable operation largely depends on the depletion conditions of the silicon channel according to charge amount stored in the floating gates and the negative control gate voltages applied for read operation. We used Silvaco Atlas, a 2D numerical simulation tool as the device simulator.

• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.36 no.4
• /
• pp.71-76
• /
• 2013

For a die casting mold, generally, the casting layout design should be considered based on the relation among injection system, casting condition, gate system, and cooling system. Also, the extent or the location of product defects was differentiated according to the various relations of the above conditions. In this research, in order to optimize the casting layout design of an automotive Oil Pan_DX2E, Computer Aided Engineering (CAE) simulation was performed with two layout designs by using the simulation software (AnyCasting). The simulation results were analyzed and compared carefully in order to apply them into the production die-casting mold. During the filling process with two models, internal porosities caused by air entrapments were predicted and also compared with the modification of the gate system and overflow. With the solidification analysis, internal porosities occurring during the solidification process were predicted and also compared with the modified gate system.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2016.02a
• /
• pp.287.2-287.2
• /
• 2016

Silicon has considerably good characteristics on electron, hole mobility and its price. With 2-D sinlge-layer Graphene/n-Si heterojunction solar cell shows that in one sun condition exhibit power conversion efficiency(PCE) of 10.1%. This photovoltaic effect was achieved by applying gate voltage to the Schottky junction of the heterostructure solar cell. Energy band diagram shows that Schottky barrier between Si and graphene can be adjust by the external electric field. because of the fermi level of the graphene can be changed by external gate voltage, we can control the Schottkky barrier of the heterostructure solar cell. The ratio between generated power of solar cell and consumption electrical power is remarkable. Since we use the graphene as the top gate electrode, most of the sun light can penetrate into the active area.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2004.08a
• /
• pp.1046-1048
• /
• 2004

Performances of organic thin film transistors (OTFTs) can be detrimentally affected by the state of the gate dielectric. Because of the bad stability of polymers, OTFTs with polymer gate dielectrics often provide abnormal characteristics. In this study, we report the condensation effect of the polymer gate dielectric layer. For the observations of the effect of the condensation, the spin-coated polymer layers with various deposition conditions were fabricated and left under low vacuum condition for several days. It is observed that the thickness of polymer layer and the electrical characteristic of OTFTs vary with the condensation time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.83-83
• /
• 2009

We studied about the effect of newly developed etchant for spacer etch process in gate patterning. With the 110nm CMOS technology, first, we changed the gate pattern size and investigated the variation of spacer etch profile according to the difference in gate length. Second, thickness of spacer nitride was changed and effect of etch ant on difference in nitride thickness was observed. In addition to these, spacer etch power was added as test item for variation of etch profile. We investigated the etch profiles with SEM and TEM analysis was used for plasma damage check. With these results we could check the process margins for gate patterning which could hold best performance and choose the condition for best spacer etch profile.

• Journal of Environmental Science International
• /
• v.14 no.11
• /
• pp.995-1004
• /
• 2005

As a research establish reservoir safety operation for small dam systems. This study presents hydrologic analysis conducted in the Duckdong and Bomun dam watershed based on various rainfall data and increase inflow. Especially the Duckdong dam without flood control feature are widely exposed to the risk of flooding, thus it is constructed emergency gate at present. In this study reservoir routing program was simulation for basin runoff estimating using HEC-HMS model, the model simulation the reservoir condition of emergency Sate with and without. At the reservoir analysis results is the Duckdong dam average storage decrease $20\%$ with emergency gate than without emergency gate. Also, the Bomun dam is not affected by the Duckdong flood control augmentation.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.1
• /
• pp.185-192
• /
• 1995

In this study, very fine photoresist pattern was examined using the image reversal process. And very fine photoriesist pattern (less than 0.2um) was obtsined by optimizing the exposure and reversal baking condition of photoresist. The produced pattern does not show the loss of thickness, and has a sparp negative edge profile. also, the ion implanted 0.25um T-shaped gate MESFET was fabricated using this resist pattern and the directional evaporation of gate metal. The fabricated MESFET has the maximum transconductance of 302 mS/mm, and the threshold voltage of -1.8V, and the drain saturation current of this MESFET was 191 mA/mm.

• Proceedings of the KSME Conference
• /
• 2000.11a
• /
• pp.492-497
• /
• 2000

This paper focuses on the weight minimization of radial gate, as an extention of the previous work. Radial gates are commonly used to regulate the flow-rate of general purpose dams, due to its simplicity in manufacture and control. The present study identifies the optimum position of support point for 2 and 3 arm type radial gate, which guarantees the minimum weight satisfying strength constraint condition. These optimum designs are then compared with previously constructed radial gates. The results indicate that the weights of the optimized radial gates reduce by about 20%, compared to those of the conventionally designed radial gates.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.12 no.6
• /
• pp.1027-1034
• /
• 2017

In this paper, we propose a new function embedding method that can measure mathematical projections of probability amplitude, probability, average expectation and matrix elements of stationary-state unit matrix at all control operation points of quantum gates. The function embedding method in this paper is to embed orthogonal normalization condition of probability amplitude for each control operating point into a binary scalar operator by using Dirac symbol and Kronecker delta symbol. Such a function embedding method is a very effective means of controlling the arithmetic power function of a unitary gate in a unitary transformation which expresses a quantum gate function as a tensor product of a single quantum. We present the results of evolutionary operation and projective measurement when we apply the proposed function embedding method to the ternary 2-qutrit cNOT gate and compare it with the existing methods.