• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.301-306
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• 2005

In this paper, a gain-boosting charge pump(CP) and a latch type voltage controlled oscillato.(VCO) with voltage controlled resistor(VCR) were proposed. The gain-boosting CP achieves good .current matching of less than 11$mu$V voltage difference between 43$mu$V and 32$mu$V in its output range from 0.8V to 2.3V. The VCO with VCR shows good linear characteristics over the range from 1V to 3V. The fabricated VCO exhibits -108dBc/Hz phase noise at a 100kHz and is comparable to that of the integrated LC-tank oscillator. The phase locked loop(PLL) with new circuits was simulated in a 0.35$mu$m CMOS process and showed 150$mu$s locking time.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.53-57
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• 2017

This paper proposes a 401MHz-406MHz low noise amplifier for MedRadio applications. The proposed low noise amplifier adopts a common gate amplifier topology using current reuse gm-boosting technique. The proposed low noise amplifier shows better performance of voltage gain and noise figure than the conventional gm-boosted common gate amplifier in the same power consumption. The proposed current-reuse gm-boosted low noise amplifier achieves a voltage gain of 22 dB, a noise figure of 2.95 dB, and IIP3 of -17 dBm while consuming $170{\mu}W$ from a 0.5 V supply voltage in $0.13{\mu}m$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.39-46
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• 2009

A fast-switching current-pulse driver for light emitting diode (LED) backlight is proposed. It uses a regulated drain current mirror (RD-CM) [1] and a high-voltage NMOS transistor (HV-NMOS). It achieves the fast-response current-pulse switching by using a dynamic gain-boosting amplifier (DGB-AMP). The DGB-AMP does not discharge the large HV-NMOS gate capacitance of the RD-CM when the output current switch turns off. Therefore, it does not need to charge the HV-NMOS gate capacitance when the switch turns on. The proposed current-pulse driver achieves the fast current switching by removing the repetitive gate discharging and charging. Simulation results were verified with measurements performed on a fabricated chip using a 5V/40V 0.5um BCD process. It reduces the switching delay to 360ns from 700ns of the conventional current-pulse driver.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.7
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• pp.1254-1259
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• 2008

A new CMOS current-mode integrator for low-voltage analog integrated circuit design is presented. The proposed current-mode integrator is based on cross-coupled gain-boosting topology. When it is compared with that of the typical current-mirror type current-mode integrator, the proposed current-mode integrator achieves high current gain and unity gain frequency with the same transistor size. As a application circuit of the proposed integrator, we designed the 1.8V 200MHz band current-mode lowpass filter. These are verified by Hspice simulation using $0.18{\mu}m$ CMOS technology.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.3
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• pp.138-144
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• 2017

In this paper, we propose a high frequency boosting circuits compensating for age-related hearing loss. The frequency response of this hearing loss is quite similar to that of a low-pass filter of which the critical frequency get lower with age. Therefore the voltage gain of this compensation circuits increase proportionally to the frequency of signals when the frequency is higher than the critical frequency and the voltage is constant irrespective of the frequency of signals when the frequency is lower than the critical frequency. The proposed circuits consist of a differential circuit and a unity gain amplifier. Because the critical frequency of the proposed circuits is controlled simply in the shape of a volume control lever, the aged people can adjust the high frequency boosting level easily according to one's hearing loss level. The critical frequency is continuously controllable in the whole audible frequency band and the gain of this high frequency boosting circuits is above 80dB at 10kHz.

• Journal of IKEEE
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• v.25 no.2
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• pp.302-308
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• 2021

A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-nm CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-V_pp differential sinusoidal analog input with frequency of 1 MHz. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.9
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• pp.825-833
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• 2016

This paper introduces a direct-conversion CMOS RF transmitter for the IEEE 802.15.4 standard with a low-power high-gain up-conversion mixer designed in $0.18{\mu}m$ process. The designed RF DCT(Direct Conversion Transmitter) is composed of differential DAC(Digital to Analog Converter), passive low-pass filter, quadrature active mixer and drive amplifier. The most important characteristic in designing RF DCT is to satisfy the 2.4 GHz Zigbee standard in low power. The quadrature active mixer inside the proposed RF DCT provides enough high gain as well as sufficient linearity using a gain boosting technique. The measurement results for the proposed transmitter show very low power consumption of 7.8 mA, output power more than 0 dBm and ACPR (Adjacent Channel Power Ratio) of -30 dBc.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1108-1110
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• 1995

This paper presents a balanced CMOS complementary folded cascode OP-AMP topology that achieves improved DC gain using the gain boosting technique, a high unity-gain frequency and improved slew rate using the CMOS complementary cascode structure and a high PSRR using the balanced output stage. Bode-plot measurements of a balanced CMOS complementary folded cascode OP-AMP show a DC gain of 80dB, a unity-gain frequency of 110MHz and a slew rate of $274V/{\mu}s$(1pF load). This balanced CMOS complementary folded cascode OP-AMP is well suited for high frequency analog signal processing applications.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1069-1073
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• 2019

In this paper, an alternative non-isolated DC-DC converter with a high voltage boosting capability is proposed. Two inductors are used and one of them has its flux linkage increases during its charging period to achieve a high step-up voltage gain. Among the three integrated capacitors, one portrays the partial characteristic of the switched-capacitor technique, while the other two are connected in series across the load. With the two switches controlled using the same duty cycle, the proposed topology demonstrates the merits of a higher and wider range of step-up voltage gain when compared with recent topologies. In addition, a reduction in loss is induced and a higher efficiency is ensured with all the voltage stresses constrained within the output voltage. Operation of the proposed converter is analyzed and validated through experimental results obtained with a prototype.

• Proceedings of the KIPE Conference
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• 2010.11a
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• pp.196-197
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• 2010

In same cases of grid connected system using photovoltaic modules, high boosting ratio is required for the converters. Four topologies based on conventional boost converters are implemented according to the voltage doubler and cascade methods. The topologies are analyzed and compared according to its boosting ratio and configurations. Consequently, the suitability of four topologies for MIC application is considered by simulation results.