1 |
Won-Hyo Lee, Jun-Dong Cho and Sung-Dae Lee, 'A high speed and low power phase-frequency detector and charge-pump', Design Automation Conf erence, 1999. Proceedings of the ASP-D AC '99. Asia and South Pacific, 18-21 Jan. 1999 , pp. 269 - 272 vol.1
|
2 |
Chan-Hong Park and B. Kim, 'A Low-No ise, 900-MHz VCO in a CMOS', IEEE J. Solid-State Circuits, 1999, May, vol. 34, pp. 586-591
DOI
ScienceOn
|
3 |
Hee-Tae Ahn, David J. Allstot, 'A Low Jitter 1.9-V CMOS PLL for UltraSPARC Microprocessor Applications', IEEE J. Solid-State Circuits, 2000, Mar., vol. 35, pp. 450-454
DOI
ScienceOn
|
4 |
IIya I. Novof, John Austin, Ram Kellar, Don Strayer and Steve Wyatt, 'Fully Integrated CMOS Phase-Locked Loop with 15 to 240MHz Locking Range and Jitter', IEEE J. Solid-State Circuits, 1995, Nov., vol. 30, pp. 1259-1266
DOI
ScienceOn
|
5 |
Behzad Razavi, Design of Analog CMOS Integrated Circuits. International Edition : McGraw-Hill 2001
|
6 |
Jae-Shin Lee, Min-Sun Keel, Shin-II Lim and Suki Kim, 'Charge pump with perfect current matching characteristics in phase-locked loops', Electronics Letters, 2000, Nov, vol. 36, pp. 1907- 1908
DOI
ScienceOn
|
7 |
Ian A Young, 'A PLL clock generator with 5 to 110 MHz of clock range microprosessors', IEEE J. Solid-State Circuits, 1992, Nov., vol. 27, pp. 1599-1 607
DOI
ScienceOn
|
8 |
Bram De Muer and Michel S. J. Steyaert, ,A CMOS Monolithic -Controlled Fractional-N Frequency Synthesizer for DCS-1800', IEEE J. Solid-State Circuits, 2002, Jul., vol. 37, pp. 835-844
DOI
ScienceOn
|
9 |
Tai-Cheng Lee and Behzad Razavi.: 'A Stabilization technique for Phase-Locked Frequency Synthesizers', IEEE J. Solid State Circuits, June 2003, vol. 38, NO. 6, pp. 888-894
DOI
ScienceOn
|