• ETRI Journal
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• v.34 no.2
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• pp.284-287
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• 2012

Quantum-dot cellular automata (QCA) is one of the few alternative computing platforms that has the potential to be a promising technology because of higher speed, smaller size, and lower power consumption in comparison with CMOS technology. This letter proposes an optimized full comparator for implementation in QCA. The proposed design is compared with previous works in terms of complexity, area, and delay. In comparison with the best previous full comparator, our design has 64% and 85% improvement in cell count and area, respectively. Also, it is implemented with only one clock cycle. The obtained results show that our full comparator is more efficient in terms of cell count, complexity, area, and delay compared to the previous designs. Therefore, this structure can be simply used in designing QCA-based circuits.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.429-432
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• 2017

In this paper, a full - wave rectifying harvesting circuit with a high-performance comparator is designed. Designed circuits are divided into Negative Voltage Converter and Active Diode stages. The comparator included in the active diode stage is implemented as a 3-stage type and divided into pre-amplification, decision circuit, and output buffer stages. The main purpose of this comparator is to reduce the propagation delay and improve the voltage and power efficiency of the harvesting circuit. The proposed circuit is designed with magna $0.35{\mu}m$ CMOS process and its operation is verified by simulation. The chip area of the designed energy harvesting circuit is $900{\mu}m{\times}712{\mu}m$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.425-428
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• 2017

This paper describes a full-wave rectifiers for energy harvesting circuit using a vibrational energy. The designed circuit is applied to the negative voltage converter with the body-bias technique using the Beta-multiplier so that the power efficiency is excellent even at the low voltage, and the comparator is designed as the bulk-driven type. The proposed circuit is designed with $0.35{\mu}m$ CMOS process, and The designed chip occupies $931{\mu}m{\times}785{\mu}m$.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.3
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• pp.529-536
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• 2019

In order to apply a piezoelectric energy harvester to a smart sensor system, an energy harvest interface circuit including an AC-DC rectifier is required. In this paper, we compared the performance of full bridge rectifier, which is a typical energy harvester interface circuit, and synchronous piezoelectric energy harvest interface circuit by using board-level simulation. As a result, the output power of a synchronous electric charge extraction(: SECE) circuit is about four times larger than that of the full bridge rectifier, and there is little load variation. And a high voltage comparator, which is essential for the SECE circuit for the piezoelectric energy harvester with an output voltage of 40V or more, was designed using 0.35 um BCD process. The SECE circuit using the designed high-voltage comparator proved that the output power is 427 % higher than the FBR circuit.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.126-134
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• 1990

In order to implement high-speed data acquistion system in CMOS VLSI technology, means must be found to overcome the relatively low transconductance and large device mismatch characteristic of MOS device. Because of these device limitations, circuit design approaches tradition-ally used in high-speed bipolar analog-to-digital converter(ADC) are suited to CMOS implementation. Also the design of VLSI CMOS comparator wherein voltage comparision is accomplished by means of a pipelined cascade RSA (Regenerative Sense Amplifier). So, in this paper we designed the A/D converter incorporates the pipelined CMOS comparator.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.278-281
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• 2014

This paper presents the performance comparison of three types of full-wave rectifiers for vibration energy harvesting. The first rectifier is consisted of two active diodes and two MOSFETs, and the comparators of the active diodes are powered from the output of the rectifier. The second one is a 2-stage full-wave rectifier. It comprises the basic rectifier consisted of four MOSFETs and an active diode. The comparator is also powered from the output of the rectifier. The third one is an input powered rectifier. It has the same structure as the second rectifier, but the comparator is powered from the input of the rectifier. These rectifiers have been designed using a 0.35um CMOS process and their performances have been compared through simulations. In terms of efficiency, the first rectifier shows the best performance at heavy loads, but the second one is suitable at light loads. When the power consumption during absence of vibration is more important than efficiency, the input-powered rectifier is proper.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.22-28
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• 2008

This paper designed a efficient 8-bit CMOS analog-to-digital converter(ADC) for an SOC(System On Chip) application. The architecture consists of two modified 4-bit full-flash ADCs, it has been designed using a more efficient architecture. This is to predict roughly the range in which input signal residers and can be placed in the proximity of input signal based on initial prediction. The prediction of input signal is made available by introducing a voltage estimator. For 4-bit resolution, the modified full-flash ADC need only 6 comparators. So a 8-bit ADC require only 12 comparators and 32 resistors. The speed of this ADC is almost similar to conventional full-flash ADC, but the die area consumption is much less due to reduce numbers of comparators and registors. This architecture uses even fewer comparator than half-flash ADC. The circuits which are implemented in this paper is simulated with LT SPICE tool of computer.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.421-424
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• 2017

This paper describes a full-wave rectifiers for energy harvesting circuit using vibration detector. The designed circuit operates only when the vibration is detected through the vibration detector and the active diode. When there is no vibration, the comparator is turned off to prevent leakage of energy stored in the $C_{STO}$. The energy stored in the capacitor is used to drive the level converter and the active diode. The energy stored in the capacitor is supplied to an active diode designed as an output power. The vibration detector is implemented with Schmitt Trigger and Peak Detector with Hysteresis function. The proposed circuit is designed in a CMOS 0.35um technology and its functionality has been verified through extensive simulations. The designed chip occupies $590{\mu}m{\times}583{\mu}m$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1983-1993
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• 1993

A power-reduction technique for full-flash A/D converters is proposed. As the resolution of a full-flash A/D converter increases linearly, the number of comparators increases exponentially. The power dissipation is generally larger than other A/D converter architectures because there are many comparators, and they are operating continuously. In this proposed architecture, only a selected number of conmarators are made to operate instead of activating all the comparators of the full-flash A/D convertor. To determine whichcomparators should be activated, voltage levelfider circuits are used. A new clock driver is developed to suppress the dynamic glitch noise which is fed back into the input stage of the comparator. By using this clock driver, the glitch noise in the current source is reduced to one fourth of that when the typical clock signal is applied. The proposed architecture has been implemented with 1.2 m 5GHz BiCMOS technology. The maximum conversion speed is 350Msamples/s. and dissipates only 900mW.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.85-90
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• 2009

This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ${\mu}m$ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 mA at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 $\times$ 2.8 $mm^{2}$.