1 |
R. Compano, L. Molenkamp, and D.J. Paul, "Technology Roadmap for Nanoelectroincs," European Commission IST Programme, FET Conf., 1999.
|
2 |
"International Technology Roadmap for Semiconductors," 2011. http://www.itrs.net
|
3 |
C.S. Lent, P.D. Tougaw, and W. Porod, "Bistable Saturation in Coupled Quantum Dots for Quantum Cellular Automata," Applied Phys. Lett., vol. 62, 1993, pp. 714-716.
DOI
|
4 |
C.S. Lent et al., "Quantum Cellular Automata," Nanotechnol., vol. 4, no. 1, 1993, pp. 49-57.
DOI
ScienceOn
|
5 |
D.A. Antonelli et al., "Quantum-Dot Cellular Automata (QCA) Circuit Partitioning: Problem Modeling and Solutions," 41st ACM/IEEE Design Automata Conf., 2004, p. 363.
|
6 |
Y. Xia and K. Qiu, "Design and Application of Universal Logic Gate Based on Quantum-Dot Cellular Automata," 11th IEEE Intern. Conf. Comm. Tech. Proc., 2008, p. 335.
|
7 |
K.-M. Qiu and Y.-S. Xia, "Quantum-Dots Cellular Automata Comparator," 7th Int. ASIC Conf., 2007, p. 1297.
|
8 |
B. Lampreht et al., "Quantum-Dot Cellular Automata Serial Comparator," 11th Euromicro. Conf. Digital Syst. Design Architectures Methods Tools, 2008, p. 447.
|
9 |
Y.-S. Xia and K.-M. Qiu, "Comparator Design Based on Quantum-Dot Cellular Automata," J. Electron. Info. Technol., vol. 31, no. 6, 2009, pp. 1517-1520.
|
10 |
S. Ying, T. Pei, and L. Xiao, "Efficient Design of QCA Optimal Universal Logic Gate ULG.2 and Its Application," 1st Inter. Conf. ICCASM, 2010, p. 392.
|
11 |
K. Walus, V.S. Dimitrov, and G.A. Julliaen, "Computer Architecture Structure for Quantum Cellular Automata," 3rd IEEE Nanotech. Conf., 2003, p. 1435.
|
12 |
M.T. Niemir, Designing Digital Systems in Quantum Cellular Automata, MSc Thesis, Department of Computer Science and Engineering Notre Dame, Indiana, 2004.
|
13 |
I. Hänninen and J. Takala, "Binary Adders on Quantum-Dot Cellular Automata," J. Signal Process. Syst., vol. 58, 2008, pp. 87-103.
|
14 |
"QCADesigner," The University of British Columbia, 2011. http://www.mina.ubc.ca/qcadesigner
|