• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.2
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• pp.329-334
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• 2014

This paper proposes the hardware architecture of high performance multi-mode 2D forward transform for HEVC which has same number of cycles for processing any type of four TUs and yield high throughput. In order to make the original image which has high pixel and high resolution into highly compressed image effectively, the transform technique of HEVC supports 4 kinds of pixel units, TUs and it finds the optimal mode after performs each transform computation. As the proposed transform engine uses the common computation operator which is produced by analyzing the relationship among transform matrix coefficients, it can process every 4 kinds of TU mode matrix operation with 35cycles equally. The proposed transform block was designed by Verilog HDL and synthesized by using TSMC 0.18um CMOS processing technology. From the results of logic synthesis, the maximum operating frequency was 400MHz and total gate count was 214k gates which has the throughput of 10-Gpels/cycle with the $4k(3840{\times}2160)@30fps$ image.

• Journal of the Institute of Convergence Signal Processing
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• v.1 no.2
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• pp.177-185
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• 2000

In this paper CPLD design of cryptographic coprocessor which implements SEED algorithm is described. To satisfy trade-off between area and speed, the coprocessor has structure in which 1 round operation is divided into three subrounds and then each subround is executed using one clock. To improve clock frequency, online precomputation scheme for round key is used. To apply the coprocessor to various applications, four operating modes such as ECB, CBC, CFB, and OFB are supported. The cryptographic coprocessor is designed using Altera EPF10K100GC503-3 CPLD device and its operation is verified by encryption or decryption of text files through ISA bus interface. It consists of about 29,300 gates and performance of CPLD chip is about 44 Mbps encryption or decryption rate under 18 Mhz clock frequency and ECB mode.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.169-177
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• 2015

This paper proposes a hardware architecture for an efficient SAO(Sample Adaptive Offset) with low area for HEVC(High Efficiency Video Coding) encoder. SAO is a newly adopted technique in HEVC as part of the in-loop filter. SAO reduces mean sample distortion by adding offsets to reconstructed samples. The existing SAO requires a great deal of computational and processing time for UHD(Ultra High Definition) video due to sample by sample processing. To reduce SAO processing time, the proposed SAO hardware architecture processes four samples simultaneously, and is implemented with a 2-step pipelined architecture. In addition, to reduce hardware area, it has a single architecture for both luma and chroma components and also uses optimized and common operators. The proposed SAO hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 190k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 200MHz, it can support 4K UHD video encoding at 60fps in real time, but operates at a maximum of 250MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1056-1063
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decoder is parameterized for the code rates 1/2, 1/3 and constraint lengths 7,9, thus it has four operation nodes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency. Also, the simulation results for BER (Bit Error Rate) performance show that the Viterbi decoder has BER of $10^{-4}$ at $E_b/N_o$ of 3.6 dB when it operates with code rate 1/3 and constraints 7.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.741-744
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• 2014

This paper has analyzed threshold voltage roll-off for bottom gate voltages of asymmetric double gate(DG) MOSFET. Since the asymmetric DGMOSFET is four terminal device to be able to separately bias for top and bottom gates, the bottom gate voltage influences on threshold voltage. It is, therefore, investigated how the threshold voltage roll-off known as short channel effects is reduced with bottom gate voltage. In the pursuit of this purpose, off-current model is presented in the subthreshold region, and the threshold voltage roll-off is observed for channel length and thickness with a parameter of bottom gate voltage as threshold voltage is defined by top gate voltage that off-currnt is $10^{-7}A/{\mu}m$ per channel width. As a result to observe the threshold voltage roll-off for bottom gate voltage using this model, we know the bottom gate voltage greatly influences on threshold voltage roll-off voltages, especially in the region of short channel length and thickness.

• Korean Journal of Metals and Materials
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• v.46 no.3
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• pp.159-168
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• 2008

Thermally-evaporated 10 nm-Ni/1 nm-Ru/(30 nm or 70 nm-poly)Si structures were fabricated in order to investigate the thermal stability of Ru-inserted nickel monosilicide. The silicide samples underwent rapid thermal anne aling at $300{\sim}1,100^{\circ}C$ for 40 seconds. Silicides suitable for the salicide process were formed on the top of the single crystal and polycrystalline silicon substrates mimicking actives and gates. The sheet resistance was measured using a four-point probe. High resolution X-ray diffraction and Auger depth profiling were used for phase and chemical composition analysis, respectively. Transmission electron microscope and scanning probe microscope(SPM) were used to determine the cross-sectional structure and surface roughness. The silicide, which formed on single crystal silicon and 30 nm polysilicon substrate, could defer the transformation of $Ni_2Si $i and $NiSi_2 $, and was stable at temperatures up to $1,100^{\circ}C$ and $1,100^{\circ}C$, respectively. Regarding microstructure, the nano-size NiSi preferred phase was observed on single crystalline Si substrate, and agglomerate phase was shown on 30 nm-thick polycrystalline Si substrate, respectively. The silicide, formed on 70 nm polysilicon substrate, showed high resistance at temperatures >$700^{\circ}C$ caused by mixed microstructure. Through SPM analysis, we confirmed that the surface roughness increased abruptly on single crystal Si substrate while not changed on polycrystalline substrate. The Ru-inserted nickel monosilicide could maintain a low resistance in wide temperature range and is considered suitable for the nano-thick silicide process.

• Journal of architectural history
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• v.18 no.5
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• pp.59-80
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• 2009

The purpose of this study is to investigate the history, space structures, blueprint, and techniques of the construction of Nam-hea city walls. Nam-hea city walls were relocated in 1439 from Whagumhun-Sansung(火金峴山城) to the present site, nearby Nam-hea Um.(南海邑) The city walls were rebuilt after they were demolished during Japanese invasion on Korea in 1592 and their reconstruction was also done in 1757. At present, the city walls only partially remained due to the urbanization of the areas around them. A plane form of the City wall is a square, and the circumference os approximately 1.3km. According to the literature, the circumference of the castle walls is 2,876尺, the height is 13尺, and the width is 13尺 4寸. Hang-Kyo(鄕校). SaGikDan(社稷壇), YoeDan(厲壇), SunSo(船所) which is a harbor, as well as government and public offices such as Kaek-Sa(客舍) and Dong-Hun(東軒) existed inside the castle walls. Inside the castle walls were one well, five springs, one ditch, and one pond, and in the castle walls, four castle gates, three curved castle walls, and 590 battlements existed. The main government offices inside castle walls were composed of Kaek-Sa, Dong-Hun, and Han-Chung(鄕廳) their arrangements were as follows. Kaek-Sa was situated toward North. Dong-Hun was situated in the center of the west castle walls. The main roads were constructed to connect the North and South castle gate, and subsidiary roads were constructed to connect the East and West castle gate. The measurement used in the blueprint for castle wall was Pobaek-scale(布帛尺:1尺=46.66cm), and one side of it was 700尺. South and North gate were constructed in the center of South and North castle wall, and curved castle walls was situated there. One bastion was in the west of curved castle walls and two bastions were in the east of curved castle walls. The east gate was located in the five eighths of in the east castle wall. Two bastions were situated in the north, on bastion in the south, one bastion in the south, and four bastions in the west castle wall. The castle walls were constructed in the following order: construction of castle field, construction of castle foundation, construction of castle wall, and cover the castle foundation. The techniques used in the construction of the castle walls include timber pile(friction pile), replacement method by excavation.

• Interdisciplinary Bio Central
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• v.4 no.3
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• pp.10.1-10.12
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• 2012

Introduction: We investigated frameshift suppressor tRNAs previously reported to use five-base anticodon-codon interactions in order to provide a collection of frameshift suppressor tRNAs to the synthetic biology community and to develop modular frameshift suppressor logic devices for use in synthetic biology applications. Results and Discussion: We adapted eleven previously described frameshift suppressor tRNAs to the BioBrick cloning format, and built three genetic logic circuits to detect frameshift suppression. The three circuits employed three different mechanisms: direct frameshift suppression of reporter gene mutations, frameshift suppression leading to positive feedback via quorum sensing, and enzymatic amplification of frameshift suppression signals. In the course of testing frameshift suppressor logic, we uncovered unexpected behavior in the frameshift suppressor tRNAs. The results led us to posit a four-base binding hypothesis for the frameshift suppressor tRNA interactions with mRNA as an alternative to the published five-base binding model. Conclusion and Prospects: The published five-base anticodon/codon rule explained only 17 of the 58 frameshift suppression experiments we conducted. Our deduced four-base binding rule successfully explained 56 out of our 58 frameshift suppression results. In the process of applying biological knowledge about frameshift suppressor tRNAs to the engineering application of frameshift suppressor logic, we discovered new biological knowledge. This knowledge leads to a redesign of the original engineering application and encourages new ones. Our study reinforces the concept that synthetic biology is often a winding path from science to engineering and back again; scientific investigations spark engineering applications, the implementation of which suggests new scientific investigations.

• Journal of the Korean Institute of Traditional Landscape Architecture
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• v.28 no.3
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• pp.85-97
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• 2010

This research studied the location and the spatial composition of Pihyang-jeong zone. Pihyang-jeong is regarded as one of the five great pavilions in Chollabuk-do. Located in Taein-myeon of Jeongeup-si, Pihyang-jeong is also called as 'the number one pavilion in Honam area'. 1. There is no record regarding the first construction of Pihyang-jeong. There is only transmitting by word of mouth that the scholar Choi Chi-won had an excursion to here and composed some poetry during the age of King Heon-gang of Shilla dynasty. However, there are records that Lee Ji-gweng had expanded the humble structure in 1618, Park Sung-go repaired it in 1664 and Yoo Geun repaired it again in 1715. 2. The location of Pihyang-jeong is 'high in north and low in south' and typical 'mountain in rear and water in front'. It has Seong-hwang Mountain(189m) in the north, Hang-ga Mountain(106m) in the south, Tae Mountain(33m) in the south and an open field in the northwest. 3. The spatial composition around Pihyang-jeong is as following. Pihyang-jeong faces 'Hayeonji'(the lower side lotus pond) in the south-south-west direction. 4. The buildings around Pihyang-jeong are; Pihyang-jeong, which was the pavilion of the government official not directly in charge of government office, Hambyeok-lu in the Hayeonji and the facility for the caretaker. Pihyang-jeong is a rectangular building with double eaves and hipped-and-gabled roof. It has five rooms in the front and four rooms in the side. Hambyeok-lu had been first built in 1918 as two-storey wooden pavilion with dancheong, traditional multicolored paintwork on wooden buildings. Then it was modified into rectangular single-storey pavilion with hipped-and-gabled roof and five rooms in 1971. In 2010, it was rebuilt as a hexagonal pavilion; therefore, the present shape is completely different one from the original shape. 5. The scenic features around Pihyang-jeong are as following. There are 21 stone monuments in Pihyang-jeong zone. The fence surrounding Pihyang-jeong is a traditional Korean style crude stone fence. There are three gates in three-gates-style, each gate made with two posts and one 'matbae'(gabled) roof. Also, a stepping stone for mounting/dismounting was found in the east of Pihyang-jeong outer perimeter. 6. The water scenic feature around Pihyang-jeong is a representative case of drawing in the water from the natural pond nearby government office and building a pavilion around the water. 7. The planting around Pihyang-jeong is as following. There are Zelkova trees in the boundary perimeter. In the southern small park, there are Zelkova trees, Crape-myrtie trees, Bushy young pine trees, Pine trees, Satuki, Purple azalea and Grass field. Around Hambyeok-lu in the Ha-yeonji, Elm trees, Zelkova trees and Pine trees are growing in good condition.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.93-101
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• 2001

In this paper, we propose an image downscaler used in multimedia video applications, such as DTV, TV-PIP, PC-video, camcorder, videophone and so on. The proposed image downscaler provides a scaled image of high-quality and high-performance. This paper will explain the scaling theory using two-dimensional digital filters. It is the method that removes an aliasing noise and decreases the hardware complexity, compared with Pixel-drop and Upsamling. Also, this paper will prove it improves scaling precisians and decreases the loss of data, compared with the Scaler32, the Bt829 of Brooktree, and the SAA7114H of Philips. The proposed downscaler consists of the following four blocks: line memory, vertical scaler, horizontal scaler, and FIFO memory. In order to reduce the hardware complexity, the using digital filters are implemented by the multiplexer-adder type scheme and their all the coefficients can be simply implemented by using shifters and adders. It also decreases the loss of high frequency data because it provides the wider BW of 6MHz as adding the compensation filter. The proposed downscaler is modeled by using the Verilog-HDL and the model is verified by using the Cadence simulator. After the verification is done, the model is synthesized into gates by using the Synopsys. The synthesized downscaler is Placed and routed by the Mentor with the IDEC-C632 0.65${\mu}{\textrm}{m}$ library for further IC implementation. The IC master is fixed in size by 4,500${\mu}{\textrm}{m}$$\times$4,500${\mu}{\textrm}{m}$. The active layout size of the proposed downscaler is 2,528${\mu}{\textrm}{m}$$\times$3,237${\mu}{\textrm}{m}$.