• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.53-60
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• 2009

Motion estimation for H.264/AVC video CODEC is very complex and requires a huge amount of computational efforts because it uses multiple reference frames and variable block sizes. We propose the architecture of high-performance integer-pixel motion estimation circuit based on fast algorithms for multiple reference frame selection, block matching, block mode decision and motion vector estimation. We also propose the architecture of high-performance interpolation circuit for sub-pixel motion estimation. We described the RTL circuit in Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The integer-pixel motion estimation circuit consists of 77,600 logic gates and four $32\times8\times32$-bit dual-port SRAM's. It has tile maximum operating frequency of 161MHz and can process up to 51 D1 (720$\times$480) color in go frames per second. The fractional motion estimation circuit consists of 22,478 logic gates. It has the maximum operating frequency of 200MHz and can process up to 69 1080HD (1,920$\times$1,088) color image frames per second.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.93-96
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decode. is parameterized for the code rates 1/2, 1/3 and constraint lengths 7, 9, thus it has four operation modes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.53-58
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• 2006

A Vertex Shader is designed to show more 3D graphics expressions, and to increase flexibility of the fixed function T&L (Transform and Lighting) engine. Design of this Shader is based on Vertex Shader 1.1 of DirectX 8.1 and OpenGL ARB. The Vertex Shader consists of four floating point ALUs for vectors operation. The previous 32bits floating point data type is replaced to 24bits floating point data type in order to design the Vertex Shader that consume low-power and occupy small area. A Xilinx Virtex2 300M gate module is used to verify behaviour of the core. The result of Synopsys synthesis shows that the proposed Vertex Shader performs 115MHz speed at the TSMC 0.13um process and it can operate as the rate of 12.5M Polygons/sec. It shows the complexity of 110,000 gates in the same process.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.12
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• pp.513-519
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• 2002

This paper proposes a high-speed FFT processor for orthogonal frequency-division multiplexing(OFDM) systems. The Proposed architecture uses a single-memory architecture and uses a radix-4 algorithm for high speed. The proposed memory is partitioned into four banks for high-speed computation. It uses an in-place memory strategy that stores butterfly outputs in the same memory location used by butterfly inputs. Therefore, the memory size can be reduced. The SQNR of about 80dB is achieved with 20-bit input and 20-bit twiddle factors. The architecture has been modeled by VHDL and logic synthesis has been performed using the SamsungTM 0.5㎛ SOG cell library (KG80). The implemented FFT processor consists of 98,326 gates excluding memory. It has smaller hardware than existing pipeline FFT processors for more than 1024-point FFTs. The processor can operate at 42MHz and calculate a 256-point complex FFT in 6us. It satisfies tile required processing speed of 8.4㎲ in the HomePlug standard.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.18-26
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n wireless LAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. From fixed-point modeling and Matlab simulations for various bit-widths, decoding performance and optimal hardware parameters such as fixed-point bit-width are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18-${\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of Advanced Navigation Technology
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• v.12 no.3
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• pp.215-219
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• 2008

Recently, a container shipping volume has increased dramatically and continued on a trend of rapid growth, and so the number of container handled at the port increase. therefore, it's increasing about concern of harbor automatism to save distribution costs in harbor. harbor automatism classifies into four large automatism's, gate automatism by using RFID that trailer come with burdening the container to be loaded on ships go though with RFID and Quay-Side container crane automatism that treats cargos loading on ships and automatism of CG that loads containers from yard, and automatism of container transporters that carries containers in between gates. To increase the using efficiency of harbor, detecting exact location of yard crane is very important matter. In this paper, propose about yard crane automatism applied UWB Location system and the development direction.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.123-130
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• 2016

In this paper, a high-performance arithmetic unit which can efficiently accelerate a number of algorithms for multimedia application was designed. The 3-stage pipelined arithmetic unit can execute 38 operations for complex and fixed-point data by using efficient configuration for four 16-bit by 16-bit multipliers, new sign extension method for carry-save data, and correction constant scheme to eliminate sign-extension in compression operation of multiple partial multiplication results. The arithmetic unit has about 300-MHz operating frequency and about 37,000 gates on 45nm CMOS technology and its estimated performance is 300 MCOPS(Million Complex Operations Per Second). Because the arithmetic unit has high processing rate and supports a number of operations dedicated to various applications, it can be efficiently applicable to multimedia processors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1355-1362
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• The Journal of the Korea Contents Association
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• v.7 no.2
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• pp.92-99
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• 2007

This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The primary purpose of this research is to evaluate physical implementation results rather than theoretical aspects. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip's 0.35um CMOS Process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher Processor would be essential for improving security of battery-less wireless sensor networks or RFID.

• Journal of the Korean Institute of Rural Architecture
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• v.14 no.3
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• pp.51-60
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• 2012

Gwangju Metropolitan City has implemented a creative regeneration project of Gwangju Folly in the site of Gwangju-eup Fortress as part of the Gwangju Design Biennale by inviting well-known international architects. This study examined and analyzed the characteristics of location, place, and space through actual survey. The results were as follows. Gwangju Folly were mainly located at the four gates and corners of Gwangju-eup Fortress, main entrances of Asia Culture Complex, and historical places where the May 18 Democratization Movement occurred. The common place of Gwangju Folly was a footpath and common location types were the full location of footpath width and the partial location of footpath width. For the spatial types of Gwangju Folly, the practical type which people can stay was the most common(2/3). In the partial location of footpath width, the type which people take a rest and look out over the surroundings accounted for a half. In the full location of footpath width, the gate type which people pass accounted for 2/5. However, as footpath width was minimum for walking, both partial and full occupation types were narrow in place. It influenced the image of Gwangju Folly. Gwangju Folly did not play as a figure and show architects' intentions clearly because of their narrow locations. Therefore, it is very necessary to make a plan to maintain places so that Gwangju Folly do not have a cramped image and architects' intentions become clear with citizens' cultural competence. Also, urban property which creates the identity and attraction of Gwangju continuously should be settled down through helping citizens recognize the intention and value of artistic works.