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http://dx.doi.org/10.6109/jkiice.2016.20.1.123

Hardware Design of High Performance Arithmetic Unit with Processing of Complex Data for Multimedia Processor  

Choi, Byeong-yoon (Department of Computer Engineering, Dongeui University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.20, no.1, 2016 , pp. 123-130 More about this Journal
Abstract
In this paper, a high-performance arithmetic unit which can efficiently accelerate a number of algorithms for multimedia application was designed. The 3-stage pipelined arithmetic unit can execute 38 operations for complex and fixed-point data by using efficient configuration for four 16-bit by 16-bit multipliers, new sign extension method for carry-save data, and correction constant scheme to eliminate sign-extension in compression operation of multiple partial multiplication results. The arithmetic unit has about 300-MHz operating frequency and about 37,000 gates on 45nm CMOS technology and its estimated performance is 300 MCOPS(Million Complex Operations Per Second). Because the arithmetic unit has high processing rate and supports a number of operations dedicated to various applications, it can be efficiently applicable to multimedia processors.
Keywords
arithmetic unit; complex data; new sign extension scheme; variable-length data;
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