• Bulletin of the Korean Chemical Society
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• v.35 no.10
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• pp.2941-2944
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• 2014

The electrical and mechanical properties of the plasma polymerized low dielectric constant SiCOH films were investigated. The SiCOH films were produced with tetrakis(trimethylsilyloxy)silane and cyclohexane as precursors by using a plasma enhanced chemical vapor deposition. When the deposition plasma powers were changed from 10 to 50 W, the relative dielectric constant of the SiCOH film increased from 2.09 to 2.76 and their hardness and elastic modulus were changed from 1.6 to 5.6 GPa and from 16 to 44 GPa, respectively. After thermal annealing at $500^{\circ}C$, the annealed SiCOH films showed relative dielectric constants of 1.80-2.97, a hardness of 0.45-0.6 GPa and an elastic modulus of 6-7 GPa. And then, the chemical structures of as-deposited and annealed SiCOH films were analyzed by using Fourier transform infrared spectroscopy.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.312-318
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• 2016

This paper presents a 2-6 GHz GaN HEMT power amplifier monolithic microwave integrated circuit (MMIC) with bridged-T all-pass filters and output-reactance-compensation shorted stubs using the $0.25{\mu}m$ GaN HEMT foundry process that is developed by WIN Semiconductors, Inc. The bridged-T filter is modified to mitigate the bandwidth degradation of impedance matching due to the inherent channel resistance of the transistor, and the shorted stub with a bypass capacitor minimizes the output reactance of the transistor to ease wideband load impedance matching for maximum output power. The fabricated power amplifier MMIC shows a flat linear gain of 20 dB or more, an average output power of 40.1 dBm and a power-added efficiency of 19-26 % in 2 to 6 GHz, which is very useful in applications such as communication jammers and electronic warfare systems.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.193-193
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• 2008

In this paper, a MMIC diplexer with a low pass and high pass filter are designed and fabricated using an InGaP/GaAs process. The design of this diplexer is based on its stabilization of the low insertion loss since it is important in the in-building system (IBS). The IBS integrates wire and wireless signal between the cable television (CATV) and the personal communication system. In this design, a dual-mode operation of diplexer is fabricated with the frequency of 0 Hz to 900 MHz and 1.7 GHz to 2.2 GHz for CATV and personal communication. respectively. The topolygy of the designed diplexer is based on the L-C filter. This diplexer fabricated by nanoENS Inc. which is foundry service company, was measured by using the facilities of the Kwangwoon University RFIC center. The fabricated chip size is $1.6\times1.4mm^2$ and it has abroad frequency range from 0 Hz to 2.2 GHz.

• Resources Recycling
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• v.6 no.1
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• pp.23-28
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• 1997

Iron and slag were prepared by melting mixed industrial wastes in an induction furnace. The wastes were steel can, limestone sludge, waste foundry sand, coal fly ash, and glasses. The effects of their mixing ratio on the charactenstics of the meltcd slag were investigated. The wastes were melted to slag under the constant basicity of 1.2. It was found that the major phases of the slag were P-C,S and C,AS and then ratio was determined by the mixing ratio af waste materials. The recovery of iron was about 93-95%. The feasibility of using the slag as the aggregate was confirmed by thc elution and campression tests.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2005.05a
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• pp.174-179
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• 2005

In the super slow speed die casting process, the casting defects due to melt flow should be controlled in order to obtain sound casting products. The casting defects that are caused by molten metal were cold shut formation, entrapment of air, gas, and inclusion. But the control of casting defects has been based on the experience of the foundry engineers. The calculation of simulation can produce very useful and important results. The calculation data of die casting process condition from the computer simulation by the Z-CAST is made to insure that the liquid metal is injected at the right velocity range and that the filling time is small enough to prevent premature solidification. The parameters of runner shape that affected on the optimized conditions that was calculated with simple equation were investigated. These die casting process control techniques of automobile valve body mid-plate have achieved good agreement with the experimental data of tensile strength, hardness test, and material structure photographies satisfactory results.

• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.57-63
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• 2020

Complementary metal-oxide-semiconductor (CMOS) technology is now facing a power scaling limit to increase integration density. Since 1970s, multi-valued logic (MVL) has been considered as promising alternative to resolve power scaling challenge for increasing information density up to peta-scale level by reducing the system complexity. Over the past several decades, however, a power-scalable and mass-producible MVL technology has been absent so that MVL circuit and system implementation have been delayed. Recently, compact MVL device researches incorporating multiple-switching characteristics in a single device such as 2D heterojunction-based negative-differential resistance (NDR)/transconductance (NDT) devices and quantum-dot/superlattices-based constant intermediate current have been actively performed. Meanwhile, wafer-scale, energy-efficient and variation-tolerant ternary-CMOS (T-CMOS) technology has been demonstrated through commercial foundry. In this review paper, an overview for MVL development history including recent studies will be presented. Then, the status and its future research direction of MVL technology will be discussed focusing on the T-CMOS technology for peta-scale information processing in semiconductor chip.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.1
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• pp.68-73
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• 2002

This paper presents the implementation of wide-band RFIC amplifier operating from near 50 MHz to 3 GHz using Tachyonics SiGe HBT foundry. Voltage shunt feedback is used for the flat gain and the broad band impedance matching. Initial design parameters are calculated through the low frequency small signal analysis. Since the HBT model was not available at the design time, discrete tuning board was made for fine adjustment in the low frequency range. Fabricated amplifier shows 12 dB gain with 1 dB fluctuation and P1 dB reaches 15 dBm at 850 MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.8
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• pp.764-768
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• 2002

In this paper, a double balanced gilbert cell MMIC mixer was realized in Tachyonics SiGe HBT technology. The fabricated mixer has 17 dB conversion gain, 9.8 dB noise figure, -4.2 dBm output 1 dB compression point, -27 dBc RF to IF isolation, and the good input, output matching characteristics. It draws 10 mA from a 3 V supply. The simulation and the measured results are closer to each other, which confirms accuracy of the model library and reliability of the process.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.51-57
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• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.

• Journal of Electrical Engineering and Technology
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• v.3 no.2
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• pp.271-275
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• 2008

The MAM(Megasonic Agitated Module) has been fabricated for improving the characteristics of wet etching. The characteristics of the MAM are investigated during the wet etching with and without megasonic agitation in this paper. The adoption of the MAM has improved the characteristics of wet etching, such as the etch rate, etch uniformity, and surface roughness. Especially, the etching uniformity on the entire wafer was less than ${\pm}1%$ in both cases of Si and glass. Generally, the initial root-mean-square roughness($R_{rms}$) of the single crystal silicon was 0.23nm. Roughnesses of 566nm and 66nm have been achieved with magnetic stirring and ultrasonic agitation, respectively, by some researchers. In this paper, the roughness of the etched Si surface is less than 60 nm. Wet etching of silicon with megasonic agitation can maintain nearly the original surface roughness during etching. The results verified that megasonic agitation is an effective way to improve etching characteristics of the etch rate, etch uniformity, and surface roughness and that the developed micromachining system is suitable for the fabrication of devices with complex structures.