Browse > Article
http://dx.doi.org/10.22895/jse.2020.0007

Multi-Valued Logic Device Technology; Overview, Status, and Its Future for Peta-Scale Information Density  

Kim, Kyung Rok (Department of Electrical Engineering, UNIST)
Jeong, Jae Won (Department of Electrical Engineering, UNIST)
Choi, Young-Eun (Department of Electrical Engineering, UNIST)
Kim, Woo-Seok (Department of Electrical Engineering, UNIST)
Chang, Jiwon (Department of Electrical Engineering, UNIST)
Publication Information
Journal of Semiconductor Engineering / v.1, no.1, 2020 , pp. 57-63 More about this Journal
Abstract
Complementary metal-oxide-semiconductor (CMOS) technology is now facing a power scaling limit to increase integration density. Since 1970s, multi-valued logic (MVL) has been considered as promising alternative to resolve power scaling challenge for increasing information density up to peta-scale level by reducing the system complexity. Over the past several decades, however, a power-scalable and mass-producible MVL technology has been absent so that MVL circuit and system implementation have been delayed. Recently, compact MVL device researches incorporating multiple-switching characteristics in a single device such as 2D heterojunction-based negative-differential resistance (NDR)/transconductance (NDT) devices and quantum-dot/superlattices-based constant intermediate current have been actively performed. Meanwhile, wafer-scale, energy-efficient and variation-tolerant ternary-CMOS (T-CMOS) technology has been demonstrated through commercial foundry. In this review paper, an overview for MVL development history including recent studies will be presented. Then, the status and its future research direction of MVL technology will be discussed focusing on the T-CMOS technology for peta-scale information processing in semiconductor chip.
Keywords
Multi-valued logic (MVL); peta-scale; power-scaling limit; ternary-CMOS (T-CMOS) technology;
Citations & Related Records
연도 인용수 순위
  • Reference
1 D. J. Frank. (2002, Mar.). Power-constrained CMOS scaling limits. IBM J. Res. Develop. [Online]. vol. 46, pp. 235-244. Available: https://doi.org/10.1147/rd.462.0235   DOI
2 V. V. Zhirnov. (2003, Nov.). Limits to binary logic switch scaling - a gedanken model. Proc. IEEE. [Online]. vol. 91, pp. 1934-1939. Available: https://doi.org/10.1109/JPROC.2003.818324   DOI
3 Smith, K. C. (1981, Sept.). The prospects for multivalued logic: A technology and applications view. IEEE Transactions on Computers. [Online]. C-30(9), pp. 619-634. Available: https://doi.org/10.1109/TC.1981.1675860   DOI
4 Hurst, S. L. (1984, Dec.). Multiple-valued logic-Its status and its future. IEEE transactions on Computers. [Online]. 33(12), pp. 1160-1179. Available: https://doi.org/10.1109/TC.1984.1676392   DOI
5 Esser, S. K. (2016, Sep.). Convolutional networks for fast, energy-efficient neuromorphic computing. [Online]. Proc. Natl Acad. Sci. USA. 113(41), pp. 11441-11446 Available: https://doi.org/10.1073/pnas.1604850113   DOI
6 Lennie, P. (2003, Mar.). The cost of cortical computation. [Online]. Curr. Biol. 13(6), pp. 493-497. Available: https://doi.org/10.1016/S0960-9822(03)00135-0   DOI
7 S. Okumura et. (2019, June.). A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2. VLSI Circuits. [Online].Available: https://doi.org/10.23919/VLSIC.2019.8778187
8 C.systems. (2019, May.). Wafer-scale Deep Learning. HotChips. [Online]. 31 Available:https://www.hotchips.org/hc31/HC31_1.13_Cerebras.SeanLie.v02.pdf
9 H. T. (1977, Mar.). Design of ternary COS/MOS memory and sequential circuits. IEEE Trans. Comput. [Online]. C-26(3), pp.281-288. Available: https://doi.org/10.1109/TC.1977.1674821   DOI
10 Mouftah, H. T. (1982, Dec.). Injected voltage low-power CMOS for 3-valued logic. IEE Proceedings G-Electronic Circuits and Systems. [Online]. 129(6). pp. 270-272. IET. Available: https://doi.org/10.1049/ip-g-1.1982.0047   DOI
11 Heo, Sunwoo. (2018, Dec.). Ternary full adder using multi-threshold voltage graphene barristors. IEEE Electron Device Letters. [Online]. 39(12), pp. 1948-1951. Available: https://doi.org/10.1109/LED.2018.2874055   DOI
12 A. Heung. (1985, Apr.). Depletion/enhancement CMOS for a lower power family of three-valued logic circuits. IEEE JSSC. Online]. sc-20(2). Available: https://doi.org/10.1109/JSSC.1985.1052354
13 A. Raychowdhury. (2005, Mar.). Carbon-nanotube-based voltage-mode multiple-valued logic design. IEEE Tran. Nanotech. [Online]. 4(2). Available: https://doi.org/10.1109/TNANO.2004.842068
14 S. Lin. (2011, Mar.). CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans. Nanotechnol. [Online]. 10(2), pp. 217-225. Available: https://doi.org/10.1109/TNANO.2009.2036845   DOI
15 W. Gang. (2009, Feb.). Ternary logic circuit design based on single electron transistors. J. Semiconductor. [Online]. 30(2). Available: https://iopscience.iop.org/article/10.1088/1674-4926/30/2/025011
16 Gage Hills. (2019, Aug.). Modern microprocessor built from complementary carbon nanotube transistors. Nature. [Online]. 572(7771) Pages 595-602. Available: https://doi.org/10.1038/s41586-019-1493-8   DOI
17 Karmakar. (2017, June.). Ternary logic gates using quantum dot gate FETs (QDGFETs). Silicon. [Online]. 6(3), pp. 169-178. Available: https://doi.org/10.1007/s12633-013-9175-x   DOI
18 Lee, Lynn. (2019, April.). ZnO composite nanolayer with mobility edge quantization for multi-value logic transistors. Nature communications. [Online]. 10(1), pp. 1-9. Available: https://doi.org/10.1038/s41467-019-09998-x   DOI
19 J. Shim et al. (2019, Nov.). Phosphorene/rhenium disulfide heterojunction-based negative differential resistance device for multi-valued logic. Nature Communications. [Online]. 7. Available: https://www.nature.com/articles/ncomms13413
20 Kim. Y. J. (2016, Dec.). Demonstration of complementary ternary graphene field-effect transistors. Scientific reports. [Online]. 6, 39353. Available: https://www.nature.com/articles/srep39353   DOI
21 Huang, Mingqiang. (2017, Oct.). Multifunctional high-performance van der Waals heterostructures. Nature nanotechnology. [Online]. 12(12), 1148. Available: https://doi.org/10.1038/nnano.2017.208   DOI
22 Lim, Ji‐Hye. (2019, Sep.). Double Negative Differential Transconductance Characteristic: From Device to Circuit Application toward Quaternary Inverter. Advanced Functional Materials. [Online]. 29(48), 1905540. Available: https://doi.org/10.1002/adfm.201905540   DOI
23 Lee, Sejoon. (2017, Sep.). Extraordinary Transport Characteristics and Multivalue Logic Functions in a Silicon-Based Negative-Differential Transconductance Device. Scientific reports. [Online]. 7(1), pp. 1-9. Available: https://doi.org/10.1038/s41598-017-11393-9   DOI
24 Kobashi, Kazuyoshi. (2018, July.). Multi-Valued Logic Circuits Based on Organic Anti-ambipolar Transistors. Nano letters. [Online]. 18(7), pp. 4355-4359. Available: https://doi.org/10.1021/acs.nanolett.8b01357   DOI
25 Yoo, Hocheon. (2019, May.). Negative Transconductance Heterojunction Organic Transistors and their Application to Full‐Swing Ternary Circuits. Advanced Materials. [Online]. 31(29), 1808265. Available: https://doi.org/10.1002/adma.201808265   DOI
26 Jeong, Jae Won. (2019, July.). Tunnelling-based ternary metal-oxide-semiconductor technology. Nature Electronics. [Online]. 2(7), pp. 307-312. Available: https://doi.org/10.1038/s41928-019-0272-8   DOI
27 Shin, Sunhae. (2015, July.). Compact design of low power standard ternary inverter based on OFF-state current mechanism using nano-CMOS technology. IEEE Transactions on Electron Devices. [Online]. 62(8), pp. 2396-2403. Available: https://doi.org/10.1109/TED.2015.2445823   DOI
28 Ternary digit logic circuit, by Kim, Kyung Rok. (2018, Nov 20). U.S. Patent No. 10,133,550. 20 [Online]. Available: https://patents.google.com/patent/US10133550B2/en
29 Park, B.-G, "Quantum Well Devices" in Nanoelectronic Devices, 1st ed. Singapore, 2012, pp. 222-223.
30 Shin, Sunhae. (2017, May.). CMOS-compatible ternary device platform for physical synthesis of multi-valued logic circuits. IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL). [Online]. pp. 284-289. Available: https://doi.org/10.1109/ISMVL.2017.48