• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1579-1581
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• 1996

The high temperature characteristics of SOI BMFET are analyzed by the numerical simulation and compared with MOS-gated SOI power devices at high temperatures. The proposed SOI BMFET combines bipolar operation in the on-state with unipolar FET operation in the off-state, so that it may be suitable for high temperature operation without any significant degradation of performance such as the leakage current and blocking capability. The simulation results show that SOI BMFET with a higher doped n-resurf layer is the most promising device far high temperature application as compared with MOS-gated SOI power devices, exhibiting the low on-state voltage drop as well as the excellent forward blocking capability at high temperature.

• 한국산학기술학회논문지
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• 제13권1호
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• pp.329-332
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• 2012

LED는 저 전력, 긴 수명, 고 휘도, 빠른 응답, 친환경적인 특성의 여러 장점을 갖고 있기 때문에 청색과 녹색 LED는 교통신호, 옥외 디스플레이, 백색 LED는 LCD 후면광 등의 응용 제품에 사용되고 있다. 여기서 LED의 성능을 향상하기 위하여 출력전력과 소자의 신뢰성을 높이고, 동작전압을 낮추어야 LED 칩의 고효율화가 이루어져야 하는데, 이는 에피택셜층, 표면요철, 패턴이 있는 사파이어 기판, 칩 설계의 최적화, 특수 공정의 개선 등의 기술이 우수해야 한다. 본 연구에서는 측면 에칭 기술과 절연층 삽입기술을 이용하여 사파이어 에피 웨이퍼 위에 GaN-기반 백색 LED 칩을 제작하여 그 성능을 조사하였다. LED 칩의 성능을 개선하기 위한 최적화 설계와 CBL(current blocking layer) 삽입 기술의 개선된 공정을 통하여 LED 칩 성능의 향상을 확인할 수 있었으며, 출력 전력은 광 출력 7cd, 순방향 인가전압 3.2V의 값을 얻었다. 현재의 LCD 후면광원으로 사용되고 있는 LED 칩의 출력에 비하여 성능이 개선되었으며, 의료기기 및 LCD LED TV의 후면광원으로 사용할 수 있을 것으로 기대된다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 C
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• pp.932-934
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• 1999

In this paper, the new IGBT structures with trap injection are proposed to improve switching characteristics of the conventional SOI LIGBT. The simulations are used in order to investigate the effects of the position, width and concentration of trap injection region using 2D device simulator MEDICI. And, their electrical characteristics are analyze and the optimum design parameters are extracted. As a result of simulation, the turn off time for the proposed LIGBT model A by the trap injection is $0.78{\mu}s$. And, the latch up voltage is 3.4V and forward blocking voltage is 168V which are superior to that of conventional structure. In addition, the proposed model is achieved more efficient in switching time and process effort. Therefore, It is shown that the trap injection is very effective to reduce the turn off time with a little increasing of on-state voltage drop if its design and process parameters are optimized.

• 한국전기전자재료학회논문지
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• 제15권10호
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• pp.844-850
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• 2002

Linearly graded profiles on the field area oxide are frequently used in power integrated circuits to reduce the surface electric field when power devices are operated in forward or reverse blocking modes. It is shown here that tapered windows can be made using the difference of etch rates between the bottom and the top layer of TEOS film. Annealed TEOS films are etched at a lower rate than the TEOS film without annealing Process. The fast etching layer results in window walls having slopes in the range of 25$^{\circ}$∼ 80$^{\circ}$ with respect to the wafer surface. Taper etching technique by annealing the TEOS film applies to high voltage LDMOS, which is compatible with CMOS process, due to the minimum changes in both of design rules and thermal budget.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.289-292
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• 2004

반도체 소자의 파괴 원인으로는 주로 열, 전압, 전류, 진동 및 압력 등이 있다. 이 중에서 전압과 열을 스트레스 인자로 적용하여 가속열화 시험을 진행하였다. 전압 및 열에 의한 소자의 열화정도를 파악하기 위해 현재 상용화되어 있는 Phase Control Thyristor 중 $V_{DRM}\;=\;1500V,\;V_{BRM}\;=\;1500V, \;T_{HS}\;=\;-40{\sim}125^{\circ}C$ 정도의 사양을 가지는 소자를 사용하였다. 열화에 의한 여러 가지 변동특성 중에서 소자의 순방향 및 역방향 항복특성의 변화와 누설전류의 변화에 대해 실험을 통해 알아보았다.

• 한국전기전자재료학회논문지
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• 제23권3호
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• pp.183-189
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• 2010

In this paper, the trench gate emitter switched thyristor(EST) withl trench gate electrode is proposed for improving snap-back effect which leads to a lot of problems in device applications. The parasitic thyristor which is inherent in the conventional EST is completely eliminated in this structure, allowing higher maximum controllable current densities for ESTs. The dual trench gate allows homogenous current distribution in the EST and preserves the unique feature of the gate controlled current saturation of the thyristor current. The characteristics of the 1700 V forward blocking EST obtained from two-dimensional numerical simulations (MEDICI) is described and compared with that of a conventional EST. we carried out layout, design and process of EST devices.

• 한국컴퓨터산업교육학회:학술대회논문집
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• 한국컴퓨터산업교육학회 2003년도 제4회 종합학술대회 논문집
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• pp.71-74
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• 2003

A vertical trench electrode type EST has been proposed in this paper. The proposed device considerably improve the snap-back effect which leads to a lot of problem of device applications. In this paper, the vertical dual gate Emitter Switched Thyristor(EST) with trench electrode has been proposed for improving snap-back effect. It is observed that the forward blocking voltage of the proposed device is 800V. The conventional EST of the same size were no more than 633V. Because the proposed device was constructed of trench-type electrode, the electric field moved toward trench-oxide layer, and the punch through breakdown of the proposed EST is occurred at latest.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 C
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• pp.938-940
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• 1999

We have fabricated SiC Schottky diode for high temperature applications. SiC thin film for drift region has been deposited by ICP-CVD. In order to establish metallization conditions, we have extracted the device parameters of the Schottky diode from the forward I-V characteristics and the C-V characteristics as a function of temperature. The ideality factor was varied from 2.07 to 1.15 and the barrier height was also varied from 1.26eV to 1.92eV with increase of temperature. The reverse blocking voltage was 183 V.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권8호
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• pp.463-467
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• 2000

In this paper, the new LIGBT structures with trap injection are proposed to improve switching characteristics of the conventional SOI LIGBT. The Simulations are performed in order to investigate the effects of the positiion, whidth and concentration of trap injection region with a reduced minority carrier lifetime using 2D device simulator MEDICI. Their electrical characteristics are analyzed and the optimum design parameters are extracted. As a result of simulation, the turn off time for the model A with the trap injection is $0.78\mus$. These results indicate the improvement of about 2 times compared with the conventional SOI LIGBT because trap injection prevents minority carriers which is stored in the n-drift region during turn off switching. The latching current is $1.5\times10^{-4}A/\mum$ and forward blocking voltage is 168V which are superior to those of conventional structure. It is shown that the trap injection is very effective to reduce the turn off time with a little increasing of on-state voltage drop if its design and process parameters are optimized.

• ETRI Journal
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• 제13권4호
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• pp.2-9
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• 1991

Buried-heterostructure lasers are more difficult to fabricate than weakly index guided or gain guided lasers. However, these strongly index guided structures are most suitable for a source of lightwave transmission systems. But, for conventional etched mesa buried heterostructure lasers, the regrowth of InP blocking layer is difficult and irreproducible. So, there are inevitable leakage currents flowing outside the active region resulting poor performance. To eliminate these problems, we used a planar buried heterostructure. As a results, the average threshold current was 28mA and the differential quantum efficiency was about 20% per facet for $1.3\mum$ GaInAsP/InP PBH-LD. The initial forward leakage current was not exceeding $1\muA$ and the reverse voltage for $-10\muA$ was -3V~-5V, these are improved figure of 1mA~10mA and -1V~-3V for EMBH laser diode. The chip modulation bandwidth was more than 2.4GHz for $1.5I_th$.