• 한국생산제조학회지
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• 제23권3호
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• pp.237-242
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• 2014

Recently much research are has been done into the compositions of lead-free solders. As a result, there has been a rapid increase in the number of new compositions. In the past, the properties of these new compositions were determined and verified through drop-impact tests. However, these drop tests were expensive and it took a long time to obtain a result. The main goal of this study was to establish an analytical method capable of predicting the impact life-time of a new solder composition for board-level flip chips though the application of drop simulations using LS-DYNA. Based on the reaction load obtain with LS-DYNA, the drop-impact fracture cycles were predicted. The study was performed using a Sn-3.0Ag-0.5Cu solder (305 composition). To verify the reliability of the proposed analytical method, the results of the drop-impact tests and life-time analysis were compared, and were found to be in good agreement. Thus, the new analytical method was shown to be very useful and effective.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.11-22
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• 2016

Clock skew scheduling is one of the essential steps to be carefully performed during the design process. This work addresses the clock skew optimization problem integrated with the consideration of the inter-dependent relation between the setup and hold times, and clock to-Q delay of flip-flops, so that the time margin is more accurately and reliably set aside over that of the previous methods, which have never taken the integrated problem into account. Precisely, based on an accurate flexible model of setup time, hold time, and clock-to-Q delay, we propose a stepwise clock skew scheduling technique in which at each iteration, the worst slack of setup and hold times is systematically and incrementally relaxed to maximally extend the time margin. The effectiveness of the proposed method is shown through experiments with benchmark circuits, demonstrating that our method relaxes the worst slack of circuits, so that the clock period ($T_{clk}$) is shortened by 4.2% on average, namely the clock speed is improved from 369 MHz~2.23 GHz to 385 MHz~2.33 GHz with no time violation. In addition, it reduces the total numbers of setup and hold time violations by 27.7%, 9.5%, and 6.7% when the clock periods are set to 95%, 90%, and 85% of the value of Tclk, respectively.

• 한국생산제조학회지
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• 제20권2호
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• pp.193-201
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• 2011

Recently, mechanical reliabilities including a drop test have been a hot issue. In this paper, solder balls with new components which are Sn-3.0Ag-0.5Cu and Sn-1.0Ag-0.5Cu-0.05N are introduced, and board level drop test for them are conducted under JEDEC standard in which the board with 15 flip chips is dropped as 1,500g acceleration during 0.5ms. The drop simulations are studied by using a implicit method in the ANSYS LS-DYNA, and modal analysis is made. Through both analyses, the solder balls with new components are evaluated under the drop. It is found that the maximum stress of each chip is occurred between the solder ball and the PCB, and the highest value among the maximum stresses in the chips is occurred on the chip nearest to fixed holes on the board in the drop tests and simulations.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2003년도 추계학술대회 논문집
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• pp.127-130
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• 2003

An RSFQ (Rapid Single Flux Quantum) counter can be used as a frequency divider that was an essential part of a programmable voltage standard chip. The voltage standard chip is composed of two circuit parts, a counter and an antenna Analog signal of tens to hundreds ㎓ may be applied to a finline antenna part. This analog signal can be converted to the stream of SFQ voltage pulses by a DC/SFQ circuit. The number of voltage pulses can be reduced by 2n times when they pass through a counter that is composed of n T Flip-Flops (Toggle Flip-Flop). Such a counter can be used not only as a frequency divider, but also to build a programmable voltage standard chip. So, its application range can be telecommunication, high speed RAM, microprocessor, etc. In this work, we have used Xic, WRspice, and L-meter to design an RSFQ counter. After circuit optimization, we could obtain the bias current margins of the T Flip-Flop circuit to be above 31％ Our RSFQ counter circuit designs were based on the 1 ㎄/$\textrm{cm}^2$ niobium trilayer technology.

• 대한의용생체공학회:학술대회논문집
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• 대한의용생체공학회 1998년도 추계학술대회
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• pp.55-56
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• 1998

The 3-D Fast Gradient Echo (Turbo FLASH, Turbo Fast Low Angle Shot) sequence is optimized to achieve a good T1 contrast using variable excitation flip angles. In Turbo FLASH sequence, depending on the contrast preparation scheme, various types of image contrast can be established. While proton density contrast is obtained when using a short repetition time with a short echo time and small flip angles, T1 or T2 weighting can be obtained with proper contrast preparation sequences applied before the above proton density Turbo FLASH sequence. To maximize the contrast to noise ratio while retaining a sharp impulse response (smooth frequency domain response), the excitation flip-angle pattern is optimized through simulation and experiments. The TI (the delay after the preparation sequence which is a 180 degree inversion RF pulse in the IR T1 weighted imaging case), TD (the delay time between the Turbo FLASH sequence and the next preparation), and TR are also optimized fur the best image quality. The proposed 3-D Turbo FLASH provides $1mm\times1mm\times1.5mm$ high resolution images within a reasonable 5-8 minutes of imaging time. The proposed imaging sequence has been implemented in a Medison's Magnum 1.0T system and verified through simulations as well as human volunteer imaging. The experimental results show the utility of the proposed method.

• 실천공학교육논문지
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• 제8권2호
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• pp.83-89
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• 2016

플립러닝은 공학적 원리 등 이론적 측면에 대한 개인 학습차가 있더라도 학습자 중심의 실제 문제해결 및 실습 등을 가능하게 하는 틀로서 공학교육의 심화 정도에 따라 효과적인 교수-학습을 가능하게 한다. 유공압기초실습은 공과대학 기계계열 교과과정에서 1학년 학생들이 처음 접하게 되는 실습 교과목으로 공압기기의 작동원리를 이해하고 자동화의 근간이 되는 전기시퀀스를 포함하는 여러 가지 기본회로를 실습을 통하여 익힘을 목적으로 한다. 본 과목은 전공과목의 입문에 해당하고 학생들은 전공에 대한 지식이 전무한 상태이므로 관련 전공지식을 모두 설명해야 하고, 또 실습에 필요한 지식도 설명해야 하므로 기존의 오프라인으로만 이루어지던 수업에서는 학생들이 실습할 시간이 턱없이 부족한 문제점이 있었다. 본 연구에서는 공학 전공 기초실습 교과목인 '유공압기초실습' 교과목의 효과적인 수업을 위해 '코리아텍(KOREATECH:한국기술교육대학교) 플립러닝 기본모형'에 따라 교수설계를 하여 플립러닝 교과목으로 개발하였고, 이를 사용하여 한 학기동안 수업을 실시한 후 수강생의 설문조사와 취득성적 등을 통해 플립러닝 교육의 효과를 분석하였다.

• Transactions on Electrical and Electronic Materials
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• 제9권1호
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• pp.33-37
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• 2008

This paper describes the development of a new $5.0{\times}3.2mm$ SAW filter bank which is consist of 12 L, C matching components and 4 SAW bare chips on PCB substrate with CSP technology. We improved the manufacturing cost by removing the ceramic package through direct flip bonding of $LiTaO_3$ SAW bare chip on PCB board after mounting L, C passive element on PCB board. After that we realized the hermitic sealing by laminating the epoxy film. To confirm the confidentiality and durability of the above method, we have obtained the optimum flip bonding & film laminating condition, and figured out material property and structure to secure the durability & moisture proof of PCB board. The newly developed super mini $5.0{\times}3.2mm$ filter bank shows the superior features than those of existing products in confidence, electrical, mechanical characters.

• 한국생산제조학회지
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• 제18권4호
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• pp.362-368
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• 2009

In general, circuit board assemblies experience various mechanical loadings during assembly and in actual use. The repeated cyclic bending can cause electrical failures due to circuit board cracks, solder interconnects cracks, and the component cracks. In this paper, we report on the failure characteristics of semiconductor chips under the repeated cyclic bending. We first describe a new 4-point bending tester, which is developed according to JEDEC standard No. 22B113. The performance of the tester is then estimated through actual experiments. Test results reveal that the cracks first occur on the outer balls around 20,000 cycles and gradually propagate to the inner balls where cracks are found around 70,000 cycles.

• ETRI Journal
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• 제26권1호
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• pp.1-6
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• 2004

The photonic quantum ring (PQR) laser is a three dimensional whispering gallery (WG) mode laser and has anomalous quantum wire properties, such as microampere to nanoampere range threshold currents and ${\sqrt{T}}$-dependent thermal red shifts. We observed uniform bottom emissions from a 1-kb smart pixel chip of a $32{\times}32$ InGaAs PQR laser array flip-chip bonded to a 0.35 ${\mu}m$ CMOS-based PQR laser driver. The PQR-CMOS smart pixel array, now operating at 30 MHz, will be improved to the GHz frequency range through device and circuit optimization.

• 마이크로전자및패키징학회지
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• 제18권4호
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• pp.19-25
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• 2011

현대 전자 산업에서Cu/Low-K공정의 도입을 통해 반도체 칩의 소형화 및 전기적 성능 향상이 가능해졌으나, Cu/Low-K는 기존의 반도체 제조 공정에 사용된 물질에 비해 물리적으로 매우 취약해진 단점을 가지고 있어 칩 제조 공정 과 패키지 공정에서 많은 문제를 유발하고 있다. 특히, 온도 사이클 후, Cu 층과 Low-K 유전층 사이의 박리현상은 주요 불량 현상의 하나이다. Cu/Low-K층은 플립 칩 패드의 상부에 위치하기 때문에 플립 칩이 받는 스트레스가 직접적으로 Cu/Low-K층에 영향을 주고 있다. 이런 문제를 해결하기 위한 언더필 공정이나 언더필 물질의 개선이 필요하게 되었고 특히, 플립 칩에 대한 스트레스를 줄이고 솔더 범프를 보호하기 위한 언더필의 선택이 중요하게 되었다. 90 nm Cu/Low-K 플립 칩 패키지의 온도 사이클 후 발생한 박리 문제를 적합한 언더필 선택을 통해 해결하였다.