• Journal of Internet Computing and Services
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• v.24 no.5
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• pp.37-50
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• 2023

In general, PLL or DDS are mainly used as precise and stable frequency synthesis methods. For stable operation, a PWM frequency generation algorithm was designed and implemented using FPGA. This is an algorithm that creates a frequency 8,192 times the target frequency and then performs the D flip-flop 13 times to generate multiple frequencies with a precision of 1 Hz. Using the designed algorithm, it is applied to the Berthing system for stopping trains in station. The applied product was developed and tested against the existing operating system to confirm its superior performance in terms of frequency generation accuracy.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.1-10
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• 2004

A cellular array parallel multiplier with parallel-inputs and parallel-outputs for performing the multiplication of two polynomials in the finite fields GF$(2^m)$ is presented in this paper. The presented cellular way parallel multiplier consists of three operation parts: the multiplicative operation part (MULOP), the irreducible polynomial operation part (IPOP), and the modular operation part (MODOP). The MULOP and the MODOP are composed if the basic cells which are designed with AND Bates and XOR Bates. The IPOP is constructed by XOR gates and D flip-flops. This multiplier is simulated by clock period l${\mu}\textrm{s}$ using PSpice. The proposed multiplier is designed by 24 AND gates, 32 XOR gates and 4 D flip-flops when degree m is 4. In case of using AOP irreducible polynomial, this multiplier requires 24 AND gates and XOR fates respectively. and not use D flip-flop. The operating time of MULOP in the presented multiplier requires one unit time(clock time), and the operating time of MODOP using IPOP requires m unit times(clock times). Therefore total operating time is m+1 unit times(clock times). The cellular array parallel multiplier is simple and regular for the wire routing and have the properties of concurrency and modularity. Also, it is expansible for the multiplication of two polynomials in the finite fields with very large m.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.73-82
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• 2005

Test data volume and power consumption for scan vectors are two major problems in system-on-a-chip testing. Therefore, this paper proposes a new test data compression/decompression method for low power testing. The method is based on analyzing the factors that influence test parameters: compression ratio, power reduction and hardware overhead. To improve the compression ratio and the power reduction ratio, the proposed method is based on Modified Statistical Coding (MSC), Input Reduction (IR) scheme and the algorithms of reordering scan flip-flops and reordering test pattern sequence in a preprocessing step. Unlike previous approaches using the CSR architecture, the proposed method is to compress original test data, not $T_{diff}$, and decompress the compressed test data without the CSR architecture. Therefore, the proposed method leads to better compression ratio with lower hardware overhead and lower power consumption than previous works. An experimental comparison on ISCAS '89 benchmark circuits validates the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.2
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• pp.28-34
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• 2012

Various feature extraction algorithms are widely applied to real-time image processing applications for extracting significant features from images. Feature extraction algorithms are mostly combined with image processing algorithms mostly for image tracking and recognition. Feature extraction function is used to supply feature information to the other image processing algorithms and it is mainly implemented in a preprocessing stage. Nowadays, image processing applications are faced with embedded system implementation for a real-time processing. In order to satisfy this requirement, it is necessary to reduce execution time so as to improve the performance. Reducing the time for executing a feature extraction function dose not only extend the execution time for the other image processing algorithms, but it also helps satisfy a real-time requirement. This paper explains FAST (Feature from Accelerated Segment Test algorithm) of E. Rosten and presents FPGA-based embedded hardware accelerator architecture. The proposed acceleration scheme can be implemented by using approximately 2,217 Flip Flops, 5,034 LUTs, 2,833 Slices, and 18 Block RAMs in the Xilinx Vertex IV FPGA. In the Modelsim - based simulation result, the proposed hardware accelerator takes 3.06 ms to extract 954 features from a image with $640{\times}480$ pixels and this result shows the cost effectiveness of the propose scheme.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.12-21
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• 2004

Error control is one of major concerns in many electronic systems. Experience shows that most malfunctions during system operation are caused by transient faults, which often mean abnormal signal delays that may result in violations of circuit element timing constraints. This paper presents a novel CMOS-based concurrent timing error detector that makes a flip-flop to sense and then signal whether its data has been potentially corrupted or not by a setup or hold timing violation. Designed circuit performs a quiescent supply current evaluation to determine timing violation from the input changes in relation to a clock edge. If the input is too close to the clock time, the resulting switching transient current in the detection circuit exceeds a reference threshold at the instant of the clock transition and an error is flagged. The circuit is designed with a $0.25{\mu}m$ standard CMOS technology at a 2.5 V supply voltage. The validity and effectiveness are verified through the HSPICE simulation. The simulation results in this paper shows that designed circuit can be used to detect setup and hold time violations effectively in clocked circuit element.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.25-34
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• 2000

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.454-464
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• 2002

In the ATM-PON (Asynchronous Transfer Mode-Passive Optical Network), the downstream cell transmitted by an OLT is broadcast to all ONUs. The ONU receives selectively its own cells by VP filtering. On the other hand, the upstream cell can be transmitted by ONU in the case of receiving a grant from the OLT. After providing the grant to an ONU, the OLT expects the arrival of a cell after an elapse of the equalized round trip delay. ITU-T G.983.1 recommends that one bit error is allowed between the expected arrival time and the actual arrival time at the OLT. Because the ONU processes the different delay to each type of grant (ranging, user cell, and mimi-slot grant), it is not simple to design the transmission part of ONU. In this paper, we implement a grant processor which provides the delay accurately in the ONU TC chip with the FPGA. For the given equalized delay, it deals with the delay for the cell, the byte, and the bit unit by using the shift register, the byte counter, and the D flip-flop, respectively. We verify the operation of the grant processor by the time simulation and the measurement of the optical board output.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.121-126
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• 2007

This paper describes a 9.09 Gb/s CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with Samsung $0.35{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the post layout simulation. The demultiplexer is achieved the maximum data rate of 9.09 Gb/s and the average power consumption of 69.93 mW. This circuit is expected to operate at higher speed than 9.09 Gb/s in the deep-submicron process of the high operating frequency.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.11-20
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• 1998

Testability analysis computes controllabilities and observabilities of all lines of a circuit and then evaluates fault coverage. The values of controllability and observability as well as fault coverage produced by testability analysis are used for applications of testability analysis. ITEM was evaluated as a fault coverage tool. But the values of controllability and observability at all lines of circuits must be estimated as a performance measure of testability tools for another application such as partial scan. In this paper, partial scan method based on sensitivity analysis which estimates relative improvement of detectability of circuits after scanning a flip-flop is used for performance evaluation of ITEM. Performance of ITEM, with respect to testability values on each net, has been measured by comparing ITEM and STAFAN. Partial scan performance achieved by ITEM is very similar to that of STAFAN, but ITEM takes less CPU time. Therefore ITEM is very efficient for partial scan application because ITEM runs faster for very large circuits in which execution time is critical.

• Journal of IKEEE
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• v.19 no.1
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• pp.10-17
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• 2015

In this Paper, an efficient method of FPGA based design and implementation of Sobel Edge detector block using 3-Line buffers is presented. The FPGA provides the proper and sufficient hardware for image processing algorithms with flexibility to support Sobel edge detection algorithm. A pipe-lined method is used to implement the edge detector. The proposed Sobel edge detection operator is an model using of Finite State Machine(FSM) which executes a matrix mask operation to determine the level of edge intensity through different of pixels on an image. This approach is useful to improve the system performance by taking advantage of efficient look up tables, flip-flop resources on target device. The proposed Sobel detector using 3-line buffers is synthesized with Xilinx ISE 14.2 and implemented on Virtex II xc2vp-30-7-FF896 FPGA device. Using matlab, we show better PSNR performance of proposed design in terms of 3-Line buffers utilization.