Browse > Article

An Embedded FAST Hardware Accelerator for Image Feature Detection  

Kim, Taek-Kyu (Korea Atomic Energy Research Institute)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SP / v.49, no.2, 2012 , pp. 28-34 More about this Journal
Abstract
Various feature extraction algorithms are widely applied to real-time image processing applications for extracting significant features from images. Feature extraction algorithms are mostly combined with image processing algorithms mostly for image tracking and recognition. Feature extraction function is used to supply feature information to the other image processing algorithms and it is mainly implemented in a preprocessing stage. Nowadays, image processing applications are faced with embedded system implementation for a real-time processing. In order to satisfy this requirement, it is necessary to reduce execution time so as to improve the performance. Reducing the time for executing a feature extraction function dose not only extend the execution time for the other image processing algorithms, but it also helps satisfy a real-time requirement. This paper explains FAST (Feature from Accelerated Segment Test algorithm) of E. Rosten and presents FPGA-based embedded hardware accelerator architecture. The proposed acceleration scheme can be implemented by using approximately 2,217 Flip Flops, 5,034 LUTs, 2,833 Slices, and 18 Block RAMs in the Xilinx Vertex IV FPGA. In the Modelsim - based simulation result, the proposed hardware accelerator takes 3.06 ms to extract 954 features from a image with $640{\times}480$ pixels and this result shows the cost effectiveness of the propose scheme.
Keywords
Feature extraction; hardware accelerator; FPGA; featue from accelerated segment test;
Citations & Related Records
연도 인용수 순위
  • Reference
1 C. Torres-Huitzil, M. Arias-Estrada, "An FPGA Architecture for High Speed Edge and Corner Detection," IEEE International Workshop on Computer Architectures for Machine Perception, pp. 112-116, Washington, DC, USA, 2000.
2 E. Rosten, T. Drummond, "Fusing Points and Lines for High Performance Tracking," IEEE International Conference on Computer Vision, vol. 2. Springer 1508-1515, Beijing, China, 2005.
3 B. Yu, et al. "A Corner Detection Algorithm Based on the Difference of FCC," International Conference on Computer Design and Application, vol. 4, pp. 226-229, Qinhuangdao, China, 2010.
4 W. Wang, R. D. Dony. "Evaluation of Image Corner Detectors for Hardware Implementation," Canadian Conference on Electrical and Computer Engineering, vol. 3, pp. 1285-1288, 2004.
5 F. Mokhtarian, R. Suomela, "Robust Image Corner Detection Through Curvature Scale Space," IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 20, no. 12, pp. 1376-1381. 1998.   DOI   ScienceOn
6 L.-H. Zou et al, "The Comparison of Two Typical Corner Detection Algorithms," Second International Symposium on Intelligent Information Technology Application, pp. 211-215, Shanghai, China, 2008.
7 김택규, 박기용, 김영기, "영상 특징 추출을 위한 내장형 가속기 구현," 대한전자공학회 하계종합학술대회 논문집, 제 34권, 1호, 698-701쪽, 2011년 6 월.
8 김택규, 박기용, 김영기, "하드웨어기반 실시간 특징추출을 위한 로봇 비전 가속기 설계 및 구현," 제6회 한국로봇종합학술대회 논문집, 197-200쪽, 2011년 6월.
9 D. G. Lowe, "Distinctive Image Features from Scales-invariant Keypoints," International Journal of Computer Vision, vol 60, no. 2, pp. 91-110, 2004.   DOI
10 C. Harris, and M. Stephens, "A Combined Corner and Edge Detector," Proceedings of the Fourth Alvey Vision Conference, pp. 147-151, 1988.
11 S. Smith, and J. Brady, "SUSAN-A New Approach to Low-level Image Processing," International Journal of Computer Vision, vol. 23, pp. 45-48, 1997.   DOI   ScienceOn
12 C. Claus et al, "Optimizing the SUSAN Corner Detection Algorithm for a High Speed FPGA Implementation," International Conference on Field Programmable Logic and Application, pp. 138-145, 2009.
13 L. Teixeria, W. Celes, and M. Gattass, "Accelerated Corner-detector Algorithms," in BMVC08, 2008. [Online]. Available: http://www.comp.leeds.ac.uk/bmvc2008/proceedings/paper/45.pdf
14 E. Rosten et al, "Faster and better: A Machine Learning Approach to Corner Detection," IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 32, no. 1, pp. 105-119, 2010.   DOI
15 E. Rosten, T. Drummond, "Machine Learning for High-speed Corner Detection," European Conference on Computer Vision, vol. 1, pp. 430-443, 2006.
16 M. Arias-Estrada, E. Rodriguez-Palacios, "An FPGA Co-processor for Real-Time Visual Tracking," in Proceedings of International Conference on Field-Programmable Logic and Application, pp. 710-719, 2002.
17 C. Claus, W. Stechele, A. Herkersdorf, "Autovision - a Runtime Reconfigurable MPSoC architecture for Future Driver Assistance Systems," it - Information Technology, vol. 49, no. 3, pp. 181-187, 2007.   DOI   ScienceOn