• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2637-2639
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• 2002

This paper presents the design and implementation of a baseband Modem using DSP that supports a wireless LAN. It is implemented with DSP and D/A and A/D Converters in baseband and tested without using IF and RF modules. In this paper, we have used the matched filler and DLL(delay lock loop) for synchronization. And the matched filter and the carrier recovery are directly connected. Therefore, the proposed architecture is very simple and the operation of DSP becomes fast.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.509-510
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• 2006

FLL (Frequency Locked Loop) is the core block for high-speed transceiver. It incorporates a PLL for fine locking action, and a coarse controller for coarse locking action. A coarse controller compares frequencies coarsely and is applied to detected frequency difference directly. Compare to conventional FLL, frequency is applied to proposed FLL. Proposed FLL in this paper achieves only 5 cycles for coarse lock and total frequency locking time is 5 times faster than conventional FLL. Thus, proposed FLL is more useful to Ethernet transceiver application that requires high-speed data transfer than conventional FLL. Proposed FLL is based on $0.18{\mu}m$ process.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.963-964
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• 2006

By combining a digital DLL and an analog DLL in 2-stage, an improved DLL is implemented in this paper. The proposed DLL is composed of a RDLL (Register Controlled DLL) and a conventional analog DLL. The phase comparator used in the DLL is built with sense-amp based D flip-flops for high speed operation. The proposed DLL circuits have been designed, simulated in 0.18um, 1.8V TSMC CMOS library. The implemented DLL have demonstrated the fast lock-on time of 1us and low jitter of 72ps.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.423-429
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• 2007

The clock recovery module of gap filler for satellite DMB is proposed. Proposed module sustains the output frequency of 10 MHz whether the received signal from the satellite is unstable or cut off within 0.5 sec. The advantages of this module is without frequency tuning at regular interval and low material cost. This module is fabricated by using CPLD as clock recovery IC and new type of loop filter for satisfying the fast lock time and long hold over time simultaneously. The measured performance of the fabricated module has a holdover time of 11 sec at frequency stability less than 0.01 ppm, and phase noise of -113 dBc/Hz at 100 Hz offset.

• Journal of the Korean Society for Nondestructive Testing
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• v.31 no.2
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• pp.150-156
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• 2011

In this paper, infrared thermography measurement technique has been used to develop standard measurement technique for nondestructive testing of composite materials which is widely used in aerospace industries. To increase the defect detection rate, the related experiment used the lock-in IR-thermographiy method. Therefore it is of considerable interest in the field of non-destructive testing for fast discontinuity detection by using ultrasonic lock-in infrared thermography. The result also shows that as the investigation period of light source is lengthened according to the thickness of specimen, the possibility of detecting defects gets higher as well. However, the reason why the result values were not favorable when less than 50 mHz of light source was provided is because it was difficult to detect defects as the defect parts became a state of thermal equilibrium in general when thermal diffusivity affects the entire materials.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.811-818
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• 2016

A continuous fine-tuning phase locked loop with an additional negative feedback loop has been proposed. When the phase locked loop is out-of-lock, the phase locked loop has a fast locking characteristic using the continuous band-selection loop. When the phase locked loop is near in-lock, the bandwidth is narrowed with the fine loop. The additional negative feedback loop consists of a voltage controlled oscillator, a frequency voltage converter and its internal loop filter. It serves a negative feedback function to the main phase locked loop, and improves the phase noise characteristics and the stability of the proposed phase locked loop. The additional negative feedback loop makes the continuous fine-tuning loop work stably without any voltage fluctuation in the loop filter. Measurement results of the fabricated phase locked loop in $0.18{\mu}m$ CMOS process show that the phase noise is -109.6dBc/Hz at 2MHz offset from 742.8MHz carrier frequency.

• Korean Journal of Optics and Photonics
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• v.15 no.1
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• pp.1-5
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• 2004

Tunable diode laser absorption spectroscopy was performed for analysis of the H$_2$$^{18}$ O/H$_2$$^{16}$ O isotope ratio of a water sample which was enriched by the membrane distillation method. In order to improve the signal-to-noise ratio, the wavelength modulation spectroscopic method was used with a lock-in amplifier. The fringe noise could be suppressed by using the FFT (Fast Fourier Transform) lowpass filter and the optimization of the modulation depth of the laser frequency. The maximum deviation of $\delta$-value was measured to be$\pm$4$\textperthousand$.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.87-95
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• 2014

This paper describes a dual channel receiver design for CIS interfaces. Each channel includes CTLE(Continuous Time Linear Equalizer), sampler, deserializer and clocking circuit. The clocking circuit is composed of PLL, PI and CDR. Fast lock acquisition time, short latency and better jitter tolerance are achieved by adding OSPD(Over Sampling Phase Detector) and FSM(Finite State Machine) to PI-based CDR. The CTLE removes ISI caused by channel with -6 dB attenuation and the lock acquisition time of the CDR is below 1 baud period in frequency offset under 8000ppm. The voltage margin is 368 mV and the timing margin is 0.93 UI in eye diagram using 65 nm CMOS technology.

• Journal of Internet Computing and Services
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• v.15 no.4
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• pp.125-133
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• 2014

The column-oriented database storage is a very advanced model for large-volume data analysis systems because of its superior I/O performance. Traditional data storages exploit row-oriented storage where the attributes of a record are placed contiguously in hard disk for fast write operations. However, for search-mostly datawarehouse systems, column-oriented storage has become a more proper model because of its superior read performance. Recently, solid state drive using MLC flash memory is largely recognized as the preferred storage media for high-speed data analysis systems. The features of non-volatility, low power consumption, and fast access time for read operations are sufficient grounds to support flash memory as major storage components of modern database servers. However, we need to improve traditional transaction management scheme due to the relatively slow characteristics of column compression and flash operation as compared to RAM memory. In this research, we propose a new scheme called Column-aware Multi-Version Locking (CaMVL) scheme for efficient transaction processing. CaMVL improves transaction performance by using compression lock and multi version reads for efficiently handling slow flash write/erase operation in lock management process. We also propose a simulation model to show the performance of CaMVL. Based on the results of the performance evaluation, we conclude that CaMVL scheme outperforms the traditional scheme.

• Journal of KIISE:Software and Applications
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• v.32 no.12
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• pp.1247-1259
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• 2005

This paper proposes a real-time face recognition system which detects multiple faces from low resolution video such as web-camera video. Face recognition system consists of the face detection step and the face classification step. At First, it finds face region candidates by using AdaBoost based object detection method which have fast speed and robust performance. It generates reduced feature vector for each face region candidate by using principle component analysis. At Second, Face classification used Principle Component Analysis and multi-SVM. Experimental result shows that the proposed method achieves real-time face detection and face recognition from low resolution video. Additionally, We implement the auto-tracking face recognition system using the Pan-Tilt Web-camera and radio On/Off digital door-lock system with face recognition system.