• International Journal of Precision Engineering and Manufacturing
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• 제8권1호
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• pp.73-78
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• 2007

The objective of this work was to simulate lead frame etching characteristics to optimize the etching process, Characteristics such as the etching factor and uniformity were investigated for different actual operating conditions, including pressure, distance from the nozzle tip, pipe pitch, and feed speed. The correlation between the etching and spray characteristics was analyzed to develop the etching model. Spray characteristics obtained from an experiment using a phase Doppler anemometer system were then simulated using a Monte-Carlo technique, The etching process model was coded in the Java language, The spray and etching characteristics were correlated with each other and simulated results agreed well with the measured data for a lead frame etching process, The optimal operating parameters under various conditions were successfully determined.

• 대한안전경영과학회지
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• 제17권3호
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• pp.355-362
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• 2015

There has been an increase of using Bosch Process to fabricate MEMS Device, TSV, Power chip for straight etching profile. Essentially, the interest of TSV technology is rapidly floated, accordingly the demand of Bosch Process is able to hold the prominent position for straight etching of Si or another wafers. Recently, the process to prevent under etching or over etching using EPD equipment is widely used for improvement of mechanical, electrical properties of devices. As an EPD device, the OES is widely used to find accurate end point of etching. However, it is difficult to maintain the light source from view port of chamber because of contamination caused by ion conflict and byproducts in the chamber. In this study, we adapted the SPOES to avoid lose of signal and detect less open ratio under 1 %. We use 12inch Si wafer and execute the through etching 500um of thickness. Furthermore, to get the clear EPD data, we developed an algorithm to only receive the etching part without deposition part. The results showed possible to find End Point of under 1 % of open ratio etching process.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.77-78
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• 2000

We verified the charged static electricity on LCD glass influences upon the etching uniformity of dry etching process by plasma. In the TFT-LCD manufacturing process, we mainly paid attention to eliminate the static electricity for TFT reliability. The static electricity caused the serious ununiformity of etching surface profile and etching rate in the dry etch process. Through our experiment on the made static electricity from -200V to -1000V, it was confirmed that the static electricity on LCD glass caused the etching rate variation of $1.5%{\sim}15%$. We recommend the etching process equipment for LCD manufacturing have to establish the soft X-ray exposure module system for eliminating the static electricity inside the loading and unloading chamber.

• 한국표면공학회지
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• 제29권1호
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• pp.60-72
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• 1996

A photoetching process is widely used for small and high precision parts in machinery, electronic and semi-conductor industries. One of the high precision parts, grid is very important part of digitron which use electron display, and it is fabricated by only photoetching process because of high precision. In this study, to develop high precision digitron grid, characteristics of etching solution were investigated with electrochemical test, that was potentiodynamic test and immersion test in the ferric chloride solution and added some additives. Based on the electrochemical etching test, grid was fabricated by continuous photoetching process at various etching condition. From the result of measured line width and etching depth under-cut and etching factor were calculated. For the fabrication of 25$\mu\textrm{m}$ line width, optimal etching condition was etching temperature 40~$45^{\circ}C$, spray pressure 1.5kg/$\textrm{cm}^2$ and etching time 3~4min.

• 반도체디스플레이기술학회지
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• 제19권2호
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• pp.77-81
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• 2020

Silicon wafer etching in micro electro mechanical systems (MEMS) fabrication is challenging to form 3-D structures. Well known Si-wet etch of silicon employs potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) and sodium hydroxide (NaOH). However, the existing silicon wet etching process has a fatal disadvantage that etching of the back side of the wafer is hard to avoid. In this study, a wet etching bath for 150 mm wafers was designed to prevent back-side etching of silicon wafer, and we demonstrated the optimized process recipe to have anisotropic wet etching of silicon wafer without any damage on the backside. We also presented the design of wet bath for 300 mm wafer processing as a promising process development.

• 한국재료학회지
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• 제27권9호
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• pp.501-506
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• 2017

Surface morphology and optical properties such as transmittance and haze effect of glass etched by physical and chemical etching processes were investigated. The physical etching process was carried out by pen type sandblasting process with $15{\sim}20{\mu}m$ dia. of $Al_2O_3$ media; the chemical etching process was conducted using HF-based mixed etchant. Sandblasting was performed in terms of variables such as the distance of 8 cm between the gun nozzle and the glass substrate, the fixed air pressure of 0.5bar, and the constant speed control of the specimen stage. The chemical etching process was conducted with mixed etching solution prepared by combination of BHF (Buffered Hydrofluoric Acid), HCl, and distilled water. The morphology of the glass surface after sandblasting process displayed sharp collision vestiges with nonuniform shapes that could initiate fractures. The haze values of the sandblasted glass were quantitatively acceptable. However, based on visual observation, the desirable Anti-Glare effect was not achieved. On the other hand, irregularly shaped and sharp vestiges transformed into enlarged and smooth micro-spherical craters with the subsequent chemical etching process. The curvature of the spherical crater increased distinctly by 60 minutes and decreased gradually with increasing etching time. Further, the spherical craters with reduced curvature were uniformly distributed over the etched glass surface. The haze value increased sharply up to 55 % and the transmittance decreased by 90 % at 60 minutes of etching time. The ideal haze value range of 3~7 % and transmittance value range of above 90 % were achieved in the period of 240 to 720 minutes of etching time for the selected concentration of the chemical etchant.

• 한국전기전자재료학회논문지
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• 제14권2호
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• pp.158-162
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• 2001

In this report, a new process for patterning of YBaCuO thin films, ICP(inductively coupled plasma) method, is described by comparing with existing wet etching method. Two 100㎛ wide and 2mm long YBaCuO striplines on LaAlO$_3$ substrates have been fabricated using two patterning techniques. And the properties were compared with the critical temperature and the SEM photography. Then, the critical temperatures of two samples were about 88 K, but the cross section of sample using ICP method was shaper than that using the wet etching method. ICP method can be used as a good etching technique process for patterning of YBaCuO superconductor.

• 한국전기전자재료학회논문지
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• 제14권2호
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• pp.117-122
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• 2001

In this paper, we report on photoelectrochemical etching process of 6H-SiC semiconductor wafer. The etching was performed in two-step process; anodization of SiC surface to form a deep porous layer and thermal oxidation followed by an HF dip. Etch rate of about 615${\AA}$/min was obtained during the anodization using a dilute HF(1.4wt% in H$_2$O) electrolyte with the etching potential of 3.0V. The etching rate was increased with the bias voltage. It was also found out that the adition of appropriate portion of H$_2$O$_2$ into the HF solution improves the etching rate. The etching process resulted in a higherly anisotropic etching characteristics and showed to have a potential for the fabrication of SiC devices with a novel design.

• 전자공학회논문지A
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• 제30A권1호
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• pp.16-22
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• 1993

A via-hole process for reproducible and reliable GaAs MMIC fabrication is described. The via-hole etching process consists of two step dry etching. During the first etching step a BC $I_{3}$/C $I_{2}$/Ar gas mixure is used to achieve high etch rate and small lateral etching. In the second etching step. CC $L_{2}$ $F_{2}$ gas is used to achieve selective etching of the GaAs substrate with respect to the front side metal layer. Via holes are formed from the backside of a 100$\mu$m thick GaAs substrate that has been evaporated initially with 500.angs. thick chromium and subsequently a 2000.angs. thick gold layer. The fabricated via holes are electroplated with gold (~20$\mu$m thick) to form via connections. The results show that established via-hole process is satisfactory for GaAs MMIC fabrication.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1996년도 한국자동제어학술회의논문집(국내학술편); 포항공과대학교, 포항; 24-26 Oct. 1996
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• pp.415-418
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• 1996

Etching Process, one of the most important process in semiconductor fabrication, has input control part of which components are pressure, gas flow, RF power and etc., and plasma gas which is complex and not exactly understood is used to etch wafer in etching chamber. So this process has not real-time feedback controller based on input-output relation, then it uses EPD(End Point Detection) signal to determine when to start or when to stop etching. Various type EPD controller control etching process using EPD signal obtained from optical intensity of etching chamber. In development EPD controller we concentrate on compensation of this signal intensity and setting the relative signal magnitude at first of etching. We compensate signal intensity using neural network learning method and set the relative signal magnitude using fuzzy inference method. Potential of this method which improves EPD system capability is proved by experiences.