• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.68-69
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• 2005

BTO ($BaTiO_3$) thin film is one of the high dielectric materials for high-density dynamic random access memories (DRAMs) due to its relatively high dielectric constant. It is generally known that BTO film is difficult to be etched by plasma etching, but high etch rate with good selectivity to pattern mask was required. The problem of sidewall angle also still remained to be solved in plasma etching of BTO thin film. In this study, we first examined the patterning possibility of BTO film by chemical mechanical polishing (CMP) process instead of plasma etching. The sputtered BTO film on TEOS film as a stopper layer was polished by CMP process with the self-developed $BaTiO_3$- and $TiO_2$-mixed abrasives slurries (MAS), respectively. The removal rate of BTO thin film using the$ BaTiO_3$-mixed abrasive slurry ($BaTiO_3$-MAS) was higher than that using the $TiO_2$-mixed abrasive slurry ($TiO_2$-MAS) in the same concentrations. The maximum removal rate of BTO thin film was 848 nm/min with an addition of $BaTiO_3$ abrasive at the concentration of 3 wt%. The sufficient within-wafer non-uniformity (WIWNU%)below 5% was obtained in each abrasive at all concentrations. The surface morphology of polished BTO thin film was investigated by atomic force microscopy (AFM).

• Journal of the Korean Vacuum Society
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• v.13 no.3
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• pp.120-126
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• 2004

A damage-reduced trench was investigated in view of the defect distribution along trench sidewall and bottom using high resolution transmission electron microscopy, which was formed by HBr plasma and additive gases in magnetically enhanced reactive ion etching system. Adding $O_2$ and other additive gases into HBr plasma makes it possible to eliminate sidewall undercut and lower surface roughness by forming the passivation layer of lateral etching. To reduce the RIE induced damage and obtain the fine shape trench corner rounding, we investigated the hydrogen annealing effect after trench formation. Silicon atomic migration on trench surfaces using high temperature hydrogen annealing was observed with atomic scale view. Migrated atoms on crystal surfaces formed specific crystal planes such as (111), (113) low index planes, instead of fully rounded comers to reduce the overall surface energy. We could observe the buildup of migrated atoms against the oxide mask, which originated from the surface migration of silicon atoms. Using this hydrogen annealing, more uniform thermal oxide could be grown on trench surfaces, suitable for the improvement of oxide breakdown.

• Journal of the Korean Vacuum Society
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• v.16 no.5
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• pp.366-370
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• 2007

Nano-scopic holes which are distributed densely and uniformly were fabricated on $SiO_2$ surface. Self-assembling resists were used to produce a layer of uniformly distributed parallel poly methyl methacrylate (PMMA) cylinders in a polystyrene (PS) matrix. The PMMA cylinders were degraded and removed by acetic acid rinsing. Subsequently, PS nanotemplates were fabricated. The patterned holes of PS template were approximately $8{\sim}30\;nm$ wide, 40 nm deep, and 60 nm apart. The porous PS template was used as a dry etching mask to transfer the pattern of PS template into the silicon oxide thin film during reactive ion etching (RIE) process. The sizes of the patterned holes on $SiO_2$ layer were $9{\sim}33\;nm$. After pattern transfer by RIE, uniformly distributed holes of which size were in the range of $6{\sim}22\;nm$ were fabricated on Si substrate. Sizes of the patterned holes were controllable by PMMA molecular weight.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.436-437
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• 2012

Double patterning technology (DPT) has been suggested as a promising candidates of the next generation lithography technology in FLASH and DRAM manufacturing in sub-40nm technology node. DPT enables to overcome the physical limitation of optical lithography, and it is expected to be continued as long as e-beam lithography takes place in manufacturing. Several different processes for DPT are currently available in practice, and they are litho-litho-etch (LLE), litho-etch-litho-etch (LELE), litho-freeze-litho-etch (LFLE), and self-aligned double patterning (SADP) [1]. The self-aligned approach is regarded as more suitable for mass production, but it requires precise control of sidewall space etch profile for the exact definition of hard mask layer. In this paper, we propose etch end point detection (EPD) in spacer etching to precisely control sidewall profile in SADP. Conventional etch EPD notify the end point after or on-set of a layer being etched is removed, but the EPD in spacer etch should land-off exactly after surface removal while the spacer is still remained. Precise control of real-time in-situ EPD may help to control the size of spacer to realize desired pattern geometry. To demonstrate the capability of spacer-etch EPD, we fabricated metal line structure on silicon dioxide layer and spacer deposition layer with silicon nitride. While blanket etch of the spacer layer takes place in inductively coupled plasma-reactive ion etching (ICP-RIE), in-situ monitoring of plasma chemistry is performed using optical emission spectroscopy (OES), and the acquired data is stored in a local computer. Through offline analysis of the acquired OES data with respect to etch gas and by-product chemistry, a representative EPD time traces signal is derived. We found that the SE-EPD is useful for precise control of spacer etching in DPT, and we are continuously developing real-time SE-EPD methodology employing cumulative sum (CUSUM) control chart [2].

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.05a
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• pp.101-102
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• 2006

BTO ($BaTiO_3$) thin film is one of the high dielectric materials for high-density dynamic random access memories (DRAMs) due to its relatively high dielectric constant, It is generally known that BTO film is difficult to be etched by plasma etching, but high etch rate with good selectivity to pattern mask was required. The problem of sidewall angle also still remained to be solved in plasma etching of BTO thin film. In this study, we first examined the patterning possibility of BTO film by chemical mechanical polishing (CMP) process instead of plasma etching. The sputtered BTO film on TEOS film as a stopper layer was polished by CMP process with the sell-developed $BaTiO_3$- and $TiO_2$-mixed abrasives slurries (MAS). respectively. The removal rate of BTO thin film using the $BaTiO_3$-mixed abrasive slurry ($BaTiO_3$-MAS) was higher than that using the $TiO_2$-mixed abrasive slurry ($TiO_2$-MAS) in the same concentrations. The maximum removal rate of BTO thin film was 848 nm/min with an addition of $BaTiO_3$ abrasive at the concentration of 3 wt%.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.658-658
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• 2013

Graphene is an attractive material for various device applications due to great electrical properties and chemical properties. However, lack of band gap is significant hurdle of graphene for future electrical device applications. In the past few years, several methods have been attempted to open and tune a band gap of graphene. For example, researchers try to fabricate graphene nanoribbon (GNR) using various templates or unzip the carbon nanotubes itself. However, these methods generate small driving currents or transconductances because of the large amount of scattering source at edge of GNRs. At 2009, Bai et al. introduced graphene nanomesh (GNM) structures which can open the band gap of large area graphene at room temperature with high current. However, this method is complex and only small area is possible. For practical applications, it needs more simple and large scale process. Herein, we introduce a photosensitive graphene device fabrication using CdSe QD coated nano-porous graphene (NPG). In our experiment, NPG was fabricated by thin film anodic aluminum oxide (AAO) film as an etching mask. First of all, we transfer the AAO on the graphene. And then, we etch the graphene using O2 reactive ion etching (RIE). Finally, we fabricate graphene device thorough photolithography process. We can control the length of NPG neckwidth from AAO pore widening time and RIE etching time. And we can increase size of NPG as large as 2 $cm^2$. Thin CdSe QD layer was deposited by spin coatingprocess. We carried out NPG structure by using field emission scanning electron microscopy (FE-SEM). And device measurements were done by Keithley 4200 SCS with 532 nm laser beam (5 mW) irradiation.

• Journal of the Korean Vacuum Society
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• v.19 no.4
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• pp.300-306
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• 2010

Superhydrophobic micro-nano hybrid structures were fabricated by reactive ion etching of hydrophobic polymer micro patterns using gold nanoparticles as etch masks. Micro structures of perfluoropolyether bisurethane methacrylate (PFPE) were prepared by soft-lithographic technique using polydimethylsiloxane (PDMS) molds. Water contact angles on the surfaces of various PFPE micro structures and corresponding micro-nano hybrid structures were compared to examine the effects of micro patterning and nanostructure formation in the manifestation of superhydrophobicity. The PFPE micro-nano hybrid structures exhibited a very stable superhydrophobicity, while the micro-only structures could not reach the superhydrophobicity but only showed the unstable hydrophobicity.

• Journal of Convergence for Information Technology
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• v.11 no.2
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• pp.10-15
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• 2021

In this paper, we formed perovskite (CH3NH3PbI3) thin films on glass with wet coating methods, and used various analytical techniques to discuss film thickness, surface roughness, crystallinity, composition, and optical property. The coated semiconductor material has no defects and is uniform, the surface roughness value is very small, and a high absorption rate has been observed in the visible light area. Next, in order to implement the hole shape in the organic-inorganic layer, Samples in the order of a metal mask with holes at regular intervals, a glass coated with a perovskite material, and a magnet were etched with atmospheric pressure plasma equipment. The shape of the hole formed in the perovskite material was analyzed by changing the time. It can be seen that more etching is performed as the time increases. The sample with the longest processing time was examined in more detail, and it was classified into 7 regions by the difference according to the location of the plasma.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.250-250
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• 2009

The fabricated the nanostructural patterns on the surface of SiN antireflection layer of polycrystalline Si solar cell using anodic aluminum oxide (AAO) masks in an inductively coupled plasma(ICP) etching process. The AAO nanopattern mask has the hole size of about 70~75nm and lattice constant of 100~120nm. The transferred nano-patterns were observed by the scanning electron microscope (SEM). The voltage of patterned Si solar cell enhanced.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.7
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• pp.604-610
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• 2004

Ultraviolet-nanoimprint lithography (UV-NIL) is a promising method for cost-effectively defining nanoscale structures at room temperature and low pressure. Since the resolution of transferred nanostructures depends strongly upon that of nanostamps, the nanostamp fabrication technology is a key technology to UV-NIL. In this paper, a $5\times5\times0.09$ in. quartz stamp whose critical dimension is 377 nm was fabricated using the etching process in which a Cr film was employed as a hard mask for transferring nanostructures onto the quartz plate. To effectively apply the fabricated 5-in. stamp to UV-NIL on a 4-in. Si wafer, we have proposed a new UV-NIL process using a multi-dispensing method as a way to supply resist on a wafer. Experiments have shown that the multi-dispensing method can enable UV-NIL using a large-area stamp.