• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.9
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• pp.1674-1680
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• 2009

This paper proposes an autonomous fault determination, fault zone isolation and fault restoration strategy based on the ethernet communication as a new attempt to solve the problem the of the existing central control method. In proposed method, The FRTU(Feeder Remote Terminal Unit)s on the feeder determines autonomously where the faulted zone is by exchanging the voltage and current information with neighbor FRTUs based on the network communication, and then separates the faulted zone in an nil-voltage status to make the protective device to reclose successively. In particular, the minimization of outage time and relational load balancing is archived by each interconnection switch which determines autonomously the load zone to be allocated among those zones after the sound outage zones was separated individually. Finally, to show effectiveness of the proposed fault restoration strategy, the several fault cases are simulated for the test distribution system, and the load balancing index of the proposed solution is compared with all of feasible solutions.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.5
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• pp.385-389
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• 2003

There are four main components of the CMP process: polishing pad, slurry, elastic supporter, and pad conditioner. The polishing pad is an essential component to the reproducibility of polishing uniformity in CMP process. However, the polishing pad in recently using metal CMP raised the several points of high cost caused by the increase of cycle time and the many usage of slurry. It is necessary to develop the novel polishing pad which would lead the cost reduction by the higher pad life-cycle, minimized cycle time and lower slurry usage. The characteristics of polishing pad were studied on the effects of different sets of the Polishing pad, which can be applied to metal chemical mechanical polishing process for global planarization of multilevel interconnection structure. The main purpose of this experiment is cost reduction by the increase of pad life-time, the decrease of cycle time and the lower usage of slurry through the specific hard porous structured pad design. It is confirmed that the novel polishing pad made the slurry usage decrease to 60% as well as the pad life-time increase twice with the 25% improvement of removal rate. The polishing time could be decreased and it also helped the cycle time to diminish. It can be expected that this results will help both the process throughput and the device yield to be improved.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.82-82
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• 2007

The chemical mechanical polishing (CMP) process has been widely used to obtain global planarization of multilevel interconnection process for ultra large scale. integrated circuit applications. Especially, the application of copper CMP has become an integral part of several semiconductor device and materials manufacturers. However, the low-k materials at 65nm and below device structures because of fragile property, requires low down-pressure mechanical polishing for maintaining the structural integrity of under layer during their fabrication. In this paper, we studied electrochemical mechanical polishing (ECMP) as a new planarization technology that uses electrolyte chemistry instead of abrasive slurry for copper CMP process. The current-voltage (I-V) curves were employed we investigated that how this chemical affect the process of voltage induced material removal in ECMP of Copper. This work was supported by grant No. (R01-2006-000-11275-0) from the Basic Research Program of the Korea Science.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.5
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• pp.380-384
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• 2013

In this paper, we have developed a low temperature process to make two type of paste by using $TiO_2$ nanoparticles(P25). The interconnections between substrate and $TiO_2$ films or link between particles of free-binder paste(FP1, FP2, FP3) is very poor. Therefore, the Titanium(IV) isopropoxide was added to the TP paste to improve the interconnection. Electron transport time (${\tau}_t$) and recombination time (${\tau}_r$) are analyzed by IMPS (intensity-modulated photocurrent spectroscopy) and IMVS(Intensity-modulated photovoltage spectroscopy). In the results, ${\tau}_t$ of TP paste based DSSCs (about $4.3{\times}10^{-3}$) is faster than other samples. ${\tau}_r$ is longer from $2.7{\times}10^{-2}$ s of FP2 to $3.0{\times}10^{-2}$ s of TP. A solar conversion efficiency (DSSCs) of TP is 3.54% for an incident solar energy of 100 mW $cm^{-2}$(meanwhile, 2.70% for DSSCs with FP2). The conversion efficiency is increased by 1.3 times.

• Korean Journal of Materials Research
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• v.23 no.10
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• pp.586-591
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• 2013

The printing of nanomaterials onto certain substrates is one of the key technologies behind high-speed interconnection and high-performance electronic devices. For the printing of next-generation electronic devices, a printing process which can be applied to a flexible substrate is needed. A printing process on a flexible substrate requires a lowtemperature, non-vacuum process due to the physical properties of the substrate. In this study, we obtained well-ordered Ag nanowires using modified gravure printing techniques. Ag nanowires are synthesized by a silver nitrate ($AgNO_3$) reduction process in an ethylene glycol solution. Ag nanowires were well aligned by hydrodynamic force on a micro-engraved Si substrate. With the three-dimensional structure of polydimethylsiloxane (PDMS), which has an inverse morphology relative to the micro-engraved Si substrate, the sub-micron alignment of Ag nanowires is possible. This technique can solve the performance problems associated with conventional organic materials. Also, given that this technique enables large-area printing, it has great applicability not only as a next-generation printing technology but also in a range of other fields.

• Proceedings of the KAIS Fall Conference
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• 2012.05b
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• pp.512-516
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• 2012

Recently the Korean government's green energy growth policy has been taken at the national level due to the sufficient supply of renewable energy. Some specific technique should be taken in consideration for the operation of the grid voltage and power quality management. In this case, there may have some chance of operational problems. Typical problems arise when grid-connected solar power produced by Pacific sunshine. The power flow in the reverse direction can create overvoltage on the distribution line and gives value of malfunction on the system. Line voltage and overvoltage adjustment practice can stop these symptoms occurred. Under these circumstances, this paper presents an interconnection test devices for photovoltaic(PV) systems composed of distribution system simulator, PV system simulator and control and monitoring systems using the LabVIEW S/W, and simulates the customer voltage characteristics considering the 3 parameters on the introduction capacity for PV systems, system configuration and Power factor. This paper also proposes a new calculation algorithm for voltage profile to make comparison between calculation values and test device values. The results show that the simulation results for the normal operation characteristics of PV systems which are very practical and effective.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.112-117
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• 2008

Vertical interconnection scheme using novel silicon-through-via for 3D MEMS devices or stacked package is proposed and fabricated to demonstrate its feasibility. The suggested silicon-through-via replaces electroplated copper, which is used as an interconnecting material in conventional through-via, with doped silicon. Adoption of doped silicon instead of metal eliminates thermal-mismatch-induced stress, which can make troubles in high temperature MEMS processes, such as wafer bonding and LP-CVD(low pressure chemical vapor deposition). Two silicon layers of $30{\mu}m$ thickness are stacked on the substrate. The through-via arrays with spacing $40{\mu}m$ and $50{\mu}m$ are fabricated successfully. Electrical characteristics of the through-via are measured and analyzed. The measured resistance of the silicon-through-via is $169.9\Omega$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.45-52
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• 2005

A systolic array formed by interconnecting a set of identical data-processing cells in a uniform manner is a combination of an algorithm and a circuit that implements it, and is closely related conceptually to arithmetic pipeline. High-performance computation on a large array of cells has been an important feature of systolic array. To achieve even higher degree of concurrency, it is desirable to make cells of systolic array themselves systolic array as well. The structure of systolic array with its cells consisting of another systolic array is to be called super-systolic array. This paper proposes a scalable bit-level super-systolic amy which can be adopted in the VLSI design including regular interconnection and functional primitives that are typical for a systolic architecture. This architecture is focused on highly regular computational structures that avoids the need for a large number of global interconnection required in general VLSI implementation. A bit-level super-systolic FIR filter is selected as an example of bit-level super-systolic array. The derived bit-level super-systolic FIR filter has been modeled and simulated in RT level using VHDL, then synthesized using Synopsys Design Compiler based on Hynix $0.35{\mu}m$ cell library. Compared conventional word-level systolic array, the newly proposed bit-level super-systolic arrays are efficient when it comes to area and throughput.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.78-89
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• 2013

This paper proposes a high-throughput and multi-mode quasi-cyclic (QC) low-density parity-check (LDPC) decoder based on a fully parallel structure. The proposed QC-LDPC decoder employs the fully parallel structure to provide very high throughput. The high interconnection complexity, which is the general problem in the fully parallel structure, is solved by using a broadcasting-based sum-product algorithm and proposing a low-complexity cyclic shift network. The high complexity problem, which is caused by using a large amount of check node processors and variable node processors, is solved by proposing a combined check and variable node processor (CCVP). The proposed QC-LDPC decoder can support the multi-mode decoding by proposing a routing-based interconnection network, the flexible CCVP and the flexible cyclic shift network. The proposed QC-LDPC decoder is operated at 100 MHz clock frequency. The proposed QC-LDPC decoder supports multi-mode decoding and provides 8.1 Gbps throughput for a (1944, 1620) QC-LDPC code.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.13-22
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• 2001

This paper presents three dimensional structure of RF packages and the improvement effect of its electrical characteristics when implementing RF transceivers. We divided RF modules into several subunits following each subunit function based on the partitioning algorithm which suggests a method of three dimension stacking interconnection, PAA(pad area array) interconnection and stacking of three dimensional RF package structures. 224MHz ITS(Intelligent Transportation System) RF module subdivided into subunits of functional blocks of a receiver(RX), a transmitter(TX), a phase locked loop(PLL) and power(PWR) unit, simultaneously meeting the requirements of impedance characteristic and system stability. Each sub­functional unit has its own frequency region of 224MHz, 21.4MHz, and 450KHz~DC. The signal gain of receiver and transmitter unit showed 18.9㏈, 23.9㏈. PLL and PWR modules also provided stable phase locking, constant voltages which agree with design specifications and maximize their characteristics. The RF module of three dimension stacking structure showed $48cm^3$, 76.9％ reduction in volume and 4.8cm, 28.4％ in net length, 41.8$^{\circ}C$, 37% in maximum operating temperature, respectively. We have found that three dimensional PAA package structure is able to produce high speed, high density, low power characteristics and to improve its functional characteristics by subdividing RF modules according to the subunit function and the operating frequency, and the features of physical volume, electrical characteristics, and thermal conditions compared to two dimensional RF circuit modules.