• ETRI Journal
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• v.37 no.1
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• pp.157-164
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• 2015

As GPU power consumption in smartphones increases with more advanced graphic performance, it becomes essential to estimate GPU power consumption accurately. The conventional GPU power model assumes, simply, that a GPU consumes constant power when turned on; however, this is no longer true for recent smartphone GPUs. In this paper, we propose an accurate GPU power model for smartphones, considering newly adopted dynamic voltage and frequency scaling. For the proposed GPU power model, our evaluation results show that the error rate for system power estimation is as low as 2.9%, on average, and 4.6% in the worst case.

• Journal of the Semiconductor & Display Technology
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• v.18 no.1
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• pp.123-128
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• 2019

Currently mobile services are on the verge of full commercialization ahead of 5G mobile communication (5G). The first goal could be to preempt the 5G market through realistic media services utilizing VR (Virtual Reality) and AR (Augmented Reality) technologies that users can most easily experience. Basically this movement is based on the advanced development of smart devices and high quality graphics processing computing power of mobile application processors. Accordingly, the importance of mobile GPUs is emerging and the most concern issue becomes a model for predicting the power and performance for smooth operation of high quality mobile contents. In many cases, the performance of mobile GPUs has been introduced in terms of power consumption of mobile GPUs using dynamic voltage and frequency scaling and throttling functions for power consumption and heat management. This paper introduces several studies of mobile GPU performance prediction model with user-friendly methods not like conventional power centric performance prediction models.

• Journal of the Korea Society of Computer and Information
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• v.16 no.6
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• pp.11-20
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• 2011

In this paper, we propose an optimal scheduling scheme that minimizes the energy consumption of a real-time video task on the multi-core platform supporting dynamic voltage and frequency scaling. Exploiting parallel execution on multiple cores for less energy consumption, the propose scheme allocates an appropriate number of cores to the task execution, turns off the power of unused cores, and assigns the lowest clock frequency meeting the deadline. Our experiments show that the proposed scheme saves a significant amount of energy, up to 67% and 89% of energy consumed by two previous methods that execute the task on a single core and on all cores respectively.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.1
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• pp.135-140
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• 2020

Recently, due to the rapid diffusion of intelligent systems and IoT technologies, power saving techniques in real-time embedded systems has become important. In this paper, we propose P-GA (Parallel Genetic Algorithm), a scheduling algorithm aims at reducing the power consumption of real-time systems in multi-core hybrid memory environments. P-GA improves the Proportional-Fairness (PF) algorithm devised for multi-core environments by combining the dynamic voltage/frequency scaling of the processor with the nonvolatile memory technologies. Specifically, P-GA applies genetic algorithms for optimizing the voltage and frequency modes of processors and the memory types, thereby minimizing the power consumptions of the task set. Simulation experiments show that the power consumption of P-GA is reduced by 2.85 times compared to the conventional schemes.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.8
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• pp.367-376
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• 2007

In this paper, we introduce an application-specific and adaptive power management technique for portable systems that support dynamic voltage scaling (DVS). We exploit both the idle time of multitasking systems running soft real-time tasks as well as memory- or CPU-bound code regions. Detailed power and execution time profiles guide an adaptive power manager (APM) that is linked to the operating system. A post-pass optimizer marks candidate regions for DVS by inserting calls to the APM. At runtime, the APM monitors the CPU's performance counters to dynamically determine the affinity of the each marked region. for each region, the APM computes the optimal voltage and frequency setting in terms of energy consumption and switches the CPU to that setting during the execution of the region. Idle time is exploited by monitoring system idle time and switching to the energy-wise most economical setting without prolonging execution. We show that our method is most effective for periodic workloads such as video or audio decoding. We have implemented our method in a multitasking operating system (Microsoft Windows CE) running on an Intel XScale-processor. We achieved up to 9% of total system power savings over the standard power management policy that puts the CPU in a low Power mode during idle periods.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.4 s.304
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• pp.167-176
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• 2005

This paper proposes a new power minimization technique for the frame-based multimedia signal processing. The derivation of the technique is based on the newly proposed microscopic DVS(Dynamic Voltage Scaling) method, where, the operating frequency and the supply voltage levels are dynamically controlled according to the processing requirement for each frame of multimedia data. The multimedia signal processing algorithms are also redesigned and optimized to maximize the power saving efficiency of the microscopic DVS technology. The characterization of the mean/variance distribution of the processing load in the frame-based multimedia signal processing provides the major basis not only for the optimized application of the microscopic DVS technology but also for the optimization of the multimedia algorithms. The power saying efficiency of the proposed DVS approach is experimentally tested with the algorithms of MPEG-2 video decoder and MPEG-2 AAC audio encoder on the ARM9 RISC processor. The experimental results with the diverse MPEG-2 video and audio files show The average power saving efficiencies of 50$\%$ and 30$\%$, respectively. The results also agree very well with those of the analytic derivations.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.11
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• pp.517-526
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• 2008

As the functionality of portable devices arc being enhanced and the performance is being greatly improved, power dissipations of battery driven portable devices are being increased. So, an efficient power management for reducing their power consumption is needed. In this paper, we propose a window-based DVS algorithm for MPEG Player. The proposed algorithm maintains the recently frame information and execution time received from MPEG player in window queue and dynamically adjusts (frequency, voltage) level based on window queue information. Our algorithm can be implemented in the common multimedia player as a module. We employed well-known MPlayer for the measurement of performance. The experimental result shows that the proposed algorithm reduces energy consumption by 56% on maximal performance.

• Journal of Korea Multimedia Society
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• v.13 no.10
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• pp.1423-1435
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• 2010

Building wireless sensor networks requires a constituting sensor node to consider the following limited hardware resources: a small battery lifetime limiting available power supply for the sensor node, a low-power microprocessor with a low-performance computing capability, and scarce memory resources. Despite such limited hardware resources of the sensor node, the sensor node platform needs to activate real-time sensing, guarantee the real-time processing of sensing data, and exchange data between individual sensor nodes concurrently. Therefore, in this paper, we propose an energy-efficient real-time task scheduling technique for battery-powered wireless sensor nodes. The proposed energy-efficient task scheduling technique controls the microprocessor's operating frequency and reduces the power consumption of a task by exploiting the slack time of the task when the actual execution time of the task can be less than its worst case execution time. The outcomes from experiments showed that the proposed scheduling technique yielded efficient performance in terms of guaranteeing the completion of real-time tasks within their deadlines and aiming to provide low power consumption.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.8
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• pp.2821-2839
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• 2015

Energy consumption by large computing systems has become an important research theme not only because the sources of energy are depleting fast but also due to the environmental concern. Computational grid is a huge distributed computing platform for the applications that require high end computing resources and consume enormous energy to facilitate execution of jobs. The organizations which are offering services for high end computation, are more cautious about energy consumption and taking utmost steps for saving energy. Therefore, this paper proposes a scheduling technique for Minimizing Energy consumption using Adapted Genetic Algorithm (MiE-AGA) for dependent tasks in Computational Grid (CG). In MiE-AGA, fitness function formulation for energy consumption has been mathematically formulated. An adapted genetic algorithm has been developed for minimizing energy consumption with appropriate modifications in each components of original genetic algorithm such as representation of chromosome, crossover, mutation and inversion operations. Pseudo code for MiE-AGA and its components has been developed with appropriate examples. MiE-AGA is simulated using Java based programs integrated with GridSim. Analysis of simulation results in terms of energy consumption, makespan and average utilization of resources clearly reveals that MiE-AGA effectively optimizes energy, makespan and average utilization of resources in CG. Comparative analysis of the optimization performance between MiE-AGA and the state-of-the-arts algorithms: EAMM, HEFT, Min-Min and Max-Min shows the effectiveness of the model.

• Journal of the Korea Society of Computer and Information
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• v.15 no.3
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• pp.1-10
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• 2010

As processor platforms are continuously moving toward wireless mobile systems, embedded mobile processors are expected to perform more and more powerful, and therefore the development of an efficient power management algorithm for these battery-operated mobile and handheld systems has become a critical challenge. It is well known that a memory system is a main performance limiter in the processor point of view. Although many DVFS studies have been considered for the efficient utilization of limited battery resources, recent works do not explicitly show the interaction between the processor and the memory. In this research, to properly reflect short/long-term memory access patterns of the embedded workloads in wireless mobile processors, we propose a memory buffer utilization as a new index of DVFS level prediction. The simulation results show that our solution provides 5.86% energy saving compared to the existing DVFS policy in case of memory intensive applications, and it provides 3.60% energy saving on average.