• 제목/요약/키워드: drain-source current

검색결과 249건 처리시간 0.023초

GaAs MESFET의 Source 접지상태에 따른 게이트 누설 전류 특성 (The GaAs Leakage Current Characteristics of GaAs MESFET's using Source Ground Status)

  • 원창섭;유영한;안형근;한득영
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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    • pp.263-266
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    • 2003
  • The gate leakage current is first calculated using the experimental method between gate and drain by opening source electrode. Next, the gate to drain current has been obtained with a ground source. The difference of two current has been tested and provide that the existence of another source to Schotuy barrier height against the image force lowering effect.

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Electron transport properties of Y-type zigzag branched carbon nanotubes

  • MaoSheng Ye;HangKong, OuYang;YiNi Lin;Quan Ynag;QingYang Xu;Tao Chen;LiNing Sun;Li Ma
    • Advances in nano research
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    • 제15권3호
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    • pp.263-275
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    • 2023
  • The electron transport properties of Y-type zigzag branched carbon nanotubes (CNTs) are of great significance for micro and nano carbon-based electronic devices and their interconnection. Based on the semi-empirical method combining tight-binding density functional theory and non-equilibrium Green's function, the electron transport properties between the branches of Y-type zigzag branched CNT are studied. The results show that the drain-source current of semiconducting Y-type zigzag branched CNT (8, 0)-(4, 0)-(4, 0) is cut-off and not affected by the gate voltage in a bias voltage range [-0.5 V, 0.5 V]. The current presents a nonlinear change in a bias voltage range [-1.5 V, -0.5 V] and [0.5 V, 1.5 V]. The tangent slope of the current-voltage curve can be changed by the gate voltage to realize the regulation of the current. The regulation effect under negative bias voltage is more significant. For the larger diameter semiconducting Y-type zigzag branched CNT (10, 0)-(5, 0)-(5, 0), only the value of drain-source current increases due to the larger diameter. For metallic Y-type zigzag branched CNT (12, 0)-(6, 0)-(6, 0), the drain-source current presents a linear change in a bias voltage range [-1.5 V, 1.5 V] and is symmetrical about (0, 0). The slope of current-voltage line can be changed by the gate voltage to realize the regulation of the current. For three kinds of Y-type zigzag branched CNT with different diameters and different conductivity, the current-voltage curve trend changes from decline to rise when the branch of drain-source is exchanged. The current regulation effect of semiconducting Y-type zigzag branched CNT under negative bias voltage is also more significant.

3차원적 전류 흐름을 고려한 FinFET의 기생 Source/Drain 저항 모델링 (Modeling of Parasitic Source/Drain Resistance in FinFET Considering 3D Current Flow)

  • 안태윤;권기원;김소영
    • 전자공학회논문지
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    • 제50권10호
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    • pp.67-75
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    • 2013
  • 본 논문에서는 RSD(Raised Source/Drain)구조를 가지는 FinFET에서 3차원적 전류 흐름을 고려한 소스와 드레인의 해석적 저항모델을 제시한다. FinFET은 Fin을 통해 전류가 흐르기 때문에 소스/드레인의 기생저항이 크고 채널을 포함한 전체저항에서 중요한 부분을 차지한다. 제안하는 모델은 3차원적 전류흐름을 고려하여 contact부터 channel 직전 영역까지의 소스/드레인 저항을 나타내며 contact저항과 spreading저항의 합으로 이루어져 있다. Contact저항은 전류의 흐름을 고려한 가이드라인을 통해 작은 저항의 병렬합으로 모델링되고 spreading저항은 적분을 통해 구현했다. 제안된 모델은 3D numerical solver인 Raphael의 실험결과를 통해 검증했다. 본 연구에서 제안된 기생저항 모델을 BSIM-CMG와 같은 압축모델에 구현하여 DC 및 AC 성능 예측의 정확도를 높일 수 있을 것이다.

Symmetric high voltage MOSFET의 extended source/drain 길이에 따른 전기적 특성의 고온영역 신뢰성 분석 (A study on the reliability test of Symmetric high voltage MOSFET under the extended source/drain length)

  • 임동주;최인철;노태문;구용서
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 통신소사이어티 추계학술대회논문집
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    • pp.309-312
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    • 2003
  • In this study, the electrical characteristic of Symmetric high voltage MOSFET (SHVMOSFET) for display driver IC were investigated. Measurement data are taken over range of temperature (300K-400K) and various extended drain length. In high temperature condition(>400K), drain current decreased over 20%, and specific on-resistance increased over 30% in comparison with room temperature.

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게이트가 파인 구조를 이용한 SOI MOSFET에서의 항복전압 개선 (Breakdown Voltage Improvement in SOI MOSFET Using Gate-Recessed Structure)

  • 최진혁;박영준;민홍식
    • 전자공학회논문지A
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    • 제32A권12호
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    • pp.159-165
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    • 1995
  • A gate-recessed structure is introduced to SOI MOSFET's in order to increase the source-to-drain breakdown voltage. A significant increase in the breakdown voltage is observed compared with that of a planar single source/drain SOI MOSFET without inducing the appreciable reduction of the current drivability. We have analyzed the origin of the breakdown voltage improvement by the substrate current measurements and 2-D device simulations, and shown that the breakdown voltage improvement is caused by the reductions in the impact ionization rate and the parasitic bipolar current gain.

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낮은 입력 정재파비와 잡음을 갖는 수동 및 능동 바이어스를 사용한 저잡음증폭기에 관한 연구 (LNA Design Uses Active and Passive Biasing Circuit to Achieve Simultaneous Low Input VSWR and Low Noise)

  • 전중성
    • Journal of Advanced Marine Engineering and Technology
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    • 제32권8호
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    • pp.1263-1268
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    • 2008
  • In this paper, the low noise power amplifier for GaAs FET ATF-10136 is designed and fabricated with active bias circuit and self bias circuit. To supply most suitable voltage and current, active bias circuit is designed. Active biasing offers the advantage that variations in the pinch-off voltage($V_p$) and saturated drain current($I_{DSS}$) will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets a gate-source voltage($V_{gs}$) for the desired drain voltage and drain current. Using resistive decoupling circuits, a signal at low frequency is dissipated by a resistor. This design method increases the stability of the LNA, suitable for input stage matching and gate source bias. The LNA is fabricated on FR-4 substrate with active and self bias circuit, and integrated in aluminum housing. As a results, the characteristics of the active and self bias circuit LNA implemented more than 13 dB and 14 dB in gain, lower than 1 dB and 1.1 dB in noise figure, 1.7 and 1.8 input VSWR at normalized frequency $1.4{\sim}1.6$, respectively.

Screen-printed Source and Drain Electrodes for Inkjet-processed Zinc-tin-oxide Thin-film Transistor

  • Kwack, Young-Jin;Choi, Woon-Seop
    • Transactions on Electrical and Electronic Materials
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    • 제12권6호
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    • pp.271-274
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    • 2011
  • Screen-printed source and drain electrodes were used for a spin-coated and inkjet-processed zinc-tin oxide (ZTO) TFTs for the first time. Source and drain were silver nanoparticles. Channel length was patterned using screen printing technology. Different silver nanoinks and process parameters were tested to find optimal source and drain contacts Relatively good electrical properties of a screen-printed inkjet-processed oxide TFT were obtained as follows; a mobility of 1.20 $cm^2$/Vs, an on-off current ratio of $10^6$, a Vth of 5.4 V and a subthreshold swing of 1.5 V/dec.

Avalanche Hot Source Method for Separated Extraction of Parasitic Source and Drain Resistances in Single Metal-Oxide-Semiconductor Field Effect Transistors

  • Baek, Seok-Cheon;Bae, Hag-Youl;Kim, Dae-Hwan;Kim, Dong-Myong
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제12권1호
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    • pp.46-52
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    • 2012
  • Separate extraction of source ($R_S$) and drain ($R_D$) resistances caused by process, layout variations and long term degradation is very important in modeling and characterization of MOSFETs. In this work, we propose "Avalanche Hot-Source Method (AHSM)" for simple separated extraction of $R_S$ and $R_D$ in a single device. In AHSM, the high field region near the drain works as a new source for abundant carriers governing the current-voltage relationship in the MOSFET at high drain bias. We applied AHSM to n-channel MOSFETs as single-finger type with different channel width/length (W/L) combinations and verified its usefulness in the extraction of $R_S$ and $R_D$. We also confirmed that there is a negligible drift in the threshold voltage ($V_T$) and the subthreshold slope (SSW) even after application of the method to devices under practical conditions.

비정질 실리코 박막 트랜지스터의 직렬 저항에 관한 분석 (Analysis for Series Resistance of Amorphous Silicon Thin Film Transistor)

  • Kim, Youn-Sang;Lee, Seong-Kyu;Han, Min-Koo
    • 대한전기학회논문지
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    • 제43권6호
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    • pp.951-957
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    • 1994
  • We present a new model for the series resistance of inverted-staggered amorphous silicon (a-Si) thin film transistors (TFT's) by employing the current spreading under the source and the drain contacts as well as the space charge limited current model. The calculated results based on our model have been in good agreements with the measured data over a wide range of applied voltage, gate-to-source and gate-to-drain overlap length, channel length, and operating temperature. Our model shows that the contribution of the series resistances to the current-voltage (I-V) characteristics of the a-Si TFT in the linear regime is more significant at low drain and high gate voltages, for short channel and small overlap length, and at low operating temperature, which have been verified successfully by the experimental measurements.

Current Modeling for Accumulation Mode GaN Schottky Barrier MOSFET for Integrated UV Sensors

  • Park, Won-June;Hahm, Sung-Ho
    • 센서학회지
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    • 제26권2호
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    • pp.79-84
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    • 2017
  • The drain current of the SB MOSFET was analytically modeled by an equation composed of thermionic emission and tunneling with consideration of the image force lowering. The depletion region electron concentration was used to model the channel electron concentration for the tunneling current. The Schottky barrier width is dependent on the channel electron concentration. The drain current is changed by the gate oxide thickness and Schottky barrier height, but it is hardly changed by the doping concentration. For a GaN SB MOSFET with ITO source and drain electrodes, the calculated threshold voltage was 3.5 V which was similar to the measured value of 3.75 V and the calculated drain current was 1.2 times higher than the measured.