• Journal of the Korea institute for structural maintenance and inspection
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• v.10 no.5
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• pp.163-170
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• 2006

Recently, piezocone penetration test is frequently used in order to estimate the characteristics of soft ground with standard penetration test, generally used in the past. In this study, the correlation of standard penetration test, piezocone penetration test and driving resistance of vertical drain is analyzed in order to increase the confidence for determination of soft ground depth. As the results of each zone, the relation between standard penetration test and piezocone penetration test shows qc=(1.09~1.63)N at the soft ground, determined by 5/30 N value which is decided for soft ground criteria. And qc=(1.21~1.98)N was shown at the point of compressible layer, evaluated by the preconsolidation pressure. And driving resistance of vertical drain is $65{\sim}70kgf/cm^2$ which is equal to $10kgf/cm^2$ of cone penetration resistance.

• Journal of Convergence for Information Technology
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• v.11 no.7
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• pp.104-110
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• 2021

A novel selective oxidation process has been developed for low source/drain (S/D) series resistance of the fin channel metal oxide semiconductor field effect transistor (MOSFET). Using this technique, the selective oxidation fin-channel MOSFET (SoxFET) has the gate-all-around structure and gradually enhanced S/D extension regions. The SoxFET demonstrated over 70% reduction in S/D series resistance compared to the control device. Moreover, it was found that the SoxFET behaved better in performance, not only a higher drive current but also higher transconductances with suppressing subthreshold swing and drain induced barrier lowering (DIBL) characteristics, than the control device. The saturation current, threshold voltage, peak linear transconductance, peak saturation transconductance, subthreshold swing, and DIBL for the fabricated SoxFET are 305 ㎂/㎛, 0.33 V, 13.5 𝜇S, 76.4 𝜇S, 78 mV/dec, and 62 mV/V, respectively.

• Transactions on Electrical and Electronic Materials
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• v.16 no.3
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• pp.139-141
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• 2015

Contact resistance of interface between the channel layers and various S/D electrodes was investigated by transmission line method. Different electrodes such as Ti/Au, a-IZO, and multilayer of a-IGZO/Ag/a-IGZO were compared in terms of contact resistance, using the transmission line model. The a-IGZO TFTs with a-IGZO/Ag/a-IGZO of S/D electrodes showed good performance and low contact resistance due to the homo-junction with channel layer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.464-472
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• 2001

Asymmetric n-MOSFET＇s for improving packing density have been fabricated with 0.35 ${\mu}{\textrm}{m}$ CMOS process. Electrical characteristics of asymmetric n-MOSFET show a lower saturation drain current and a higher linear resistance compared to those of symmetric devices. Substrate current of asymmetric MOSFET is lower than that of symmetric devices. Asymmetric n-MOSFET＇s have been modeled using a parasitic resistance associated with abnormally structured drain or source and a conventional n-MOSFET model. MEDICI simulation has been done for accuracy of this modeling. Simulated values of reverse as we11 as forward saturation drain current show good agreement with measured values for asymmetric device.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.3
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• pp.134-140
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• 2002

Deep submicron NMOSFETs with elevated source/drain can be fabricated using self-aligned selective epitaxial growth(SEG) of silicon for enhanced device characteristics with shallow junction compared to conventional MOSFETs. Shallow junctions, especially with the heartily-doped S/D residing in the elevated layer, give hotter immunity to Yt roll off, drain-induced-barrier-lowering (DIBL), subthreshold swing (SS), punch-through, and hot carrier effects. In this paper, the characteristics of both deep submicron elevated source/drain NMOSFETs and conventional NMOSFETs were investigated by using TSUPREM-4 and MEDICI simulators, and then the results were compared. It was observed from the simulation results that deep submicron elevated S/D NMOSFETs having shallower junction depth resulted in reduced short channel effects, such as DIBL, SS, and hot carrier effects than conventional NMOSFETs. The saturation current, Idsat, of the elevated S/D NMOSFETs was higher than conventional NMOSFETs with identical device dimensions due to smaller sheet resistance in source/drain regions. However, the gate-to-drain capacitance increased in the elevated S/D MOSFETs compared with the conventional NMOSFETs because of increasing overlap area. Therefore, it is concluded that elevated S/D MOSFETs may result in better device characteristics including current drivability than conventional NMOSFETs, but there exists trade-off between device characteristics and fate-to-drain capacitance.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.36-39
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• 2000

The adaptive learning circuit is designed the basis of modeling of MFSFET (Metal-Ferroelectric-Semiconductor FET) and the numerical results is analyzed. The output frequency of the adaptive learning circuit is inversely proportioned to the source-drain resistance of MFSFET and the capacitance of the circuit. The output frequency modulation of the adaptive learning circuit is investigated by analyzing the source-drain resistance of MFSFET as functions of imput pulse numbers in the adaptive learning circuit and the dimensionality factor of the ferroelectric thin film. From the results, the frequency modulation characteristics of the adaptive learning circuit, that is, adaptive learning characteristics which means a gradual frequency change of output pulse with the progress of input pulse are confirmed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.485-489
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• 2015

An accurate large-signal BSIM4 macro model including new empirical bias-dependent equations of the drain-source capacitance and channel resistance constructed from bias-dependent data extracted from S-parameters of RF MOSFETs is developed to reduce $S_{22}$-parameter error of a conventional BSIM4 model. Its accuracy is validated by finding the much better agreement up to 40 GHz between the measured and modeled $S_{22}$-parameter than the conventional one in the wide bias range.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.139-144
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• 2003

We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.26-29
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• 1999

The I-V characteristics of the n-channel offset gated poly-Si TETs have been systematically investigated in order to analyse the effects of offset region. The on currents are reduced due to the series resistance by the offset length and there is no kink phenomenon in offset devices. The off currents of the offset gated TFTs are remarkably reduced to 10$^{-12}$ A independent of gate and drain voltage because the electric field is weakened by the increase of the depletion region width near the drain region. It is shown that the offset regions behave as a series resistance and reduce lateral and vertical electric field.

• Magazine of the Korea Concrete Institute
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• v.28 no.3
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• pp.18-22
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• 2016