• Transactions on Electrical and Electronic Materials
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• v.16 no.5
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• pp.254-259
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• 2015

This paper reports the optimized mixed-signal performance of a high-voltage (HV) laterally double-diffused metaloxide-semiconductor (LDMOS) field-effect transistor (FET) with a dual gate oxide (DGOX). The fabricated device is based on the split-gate FET concept. In addition, the gate oxide on the source-side channel is thicker than that on the drain-side channel. The experiment results showed that the electrical characteristics are strongly dependent on the source-side channel length with a thick gate oxide. The digital and analog performances according to the source-side channel length of the DGOX LDMOS device were examined for circuit applications. The HV DGOX device with various source-side channel lengths showed reduced by maximum 37% on-resistance (R_ON) and 50% drain conductance (g_ds). Therefore, the optimized mixed-signal performance of the HV DGOX device can be obtained when the source-side channel length with a thick gate oxide is shorter than half of the channel length.

• Journal of the Korean Vacuum Society
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• v.11 no.4
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• pp.212-217
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• 2002

A new technique for highly controllable trench corner rounding at the top and bottom of the trench using pull-back and hydrogen annealing has been developed and investigated. The pull-back process could control the trench corner rounding radius at the top comers of the trench. The silicon migration generated by hydrogen annealing at the trench coiners provided (111) and (311) crystal planes and gave a uniform gate-oxide thickness, resulting in high reliable trench DMOSFETs with highly breakdown voltages and low leakage currents. The breakdown voltage of a trench DMOSFET fabricated using hydrogen annealing was increased by 25% compared with a conventional DMOSFET. The reasonable drain current of 45.3 A was obtained when a gate voltage of 10 V was supplied. The on-resistance of the trench gate DMOSFET fabricated using the trench cell of 45,000 was about 55 m(at a gate voltage of 10 V under a drain current of 5 A.

• Geotechnical Engineering
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• v.13 no.2
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• pp.39-54
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• 1997

Laboratory testings were carried out on plastic board drains (PBDs) using large scale test apparatus to evaluate the physical properties and the drainage performance. The test results reveal that the domestic products of PBDs are well compared with the foreign prod acts as far as the quality and drainage performance are concerned. It has also been confirmed that the discharge capacity decreases with time in such a way that the air bubbles are entrapped inside kinky PBDs and these air bubbles block the water flow through PBDs. It has been found that the vacuum pressure iseffectively applicable to recover the discharge capacity affected by the entrapped air bubbles.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1361-1363
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• 2005

In this paper, we report on the performance stability of solution processible OTFT devices with Au/Ti and ITO source-drain (S/D) electrodes. It appears that the contact resistance of the S/D electrode strongly affects the stability of OTFT devices. Interestingly, the devices with the Au/Ti electrode showed lower mobility than those with the ITO (S/D) devices. The field effect mobilities of the devices with the Au/Ti and ITO electrodes were 0.06, and $0.44cm^2/Vs$, respectively. However, the mobility of the device with the Au/Ti electrode was increased up to $0.26cm^2/Vs$ after 2 weeks, while the mobility of the device with ITO electrode was slightly decreased down to $0.41cm^2/Vs$. The experimental data show us that ITO could be used as the S/D electrode for low-cost OTFT devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.110-119
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• 2007

A new two-dimensional analytical model for dual-material double-gate fully-depleted SOI MOSFET with Pearson-IV type Doping Distribution is presented. An investigation of electrical MOSFET parameters i.e. drain current, transconductance, channel resistance and device capacitance in DM DG FD SOI MOSFET is carried out with Pearson-IV type doping distribution as it is essential to establish proper profiles to get the optimum performance of the device. These parameters are categorically derived keeping view of potential at the center (${\phi}_c$) of the double gate SOI MOSFET as it is more sensitive than the potential at the surface (${\phi}_s$). The proposed structure is such that the work function of the gate material (both sides) near the source is higher than the one near the drain. This work demonstrates the benefits of high performance proposed structure over their single material gate counterparts. The results predicted by the model are compared with those obtained by 2D device simulator ATLAS to verify the accuracy of the proposed model.

• Journal of the Korea Concrete Institute
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• v.12 no.6
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• pp.119-126
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• 2000

Reinforced concrete structural walls are widely known to provide an efficient lateral load resistance and drift control. However, many reported researches on them are mostly limited to the RC structural walls reinforced according to seismic details. When the pushover analysis technique is used for the prediction of inelastic behavior of frame-wall structures for the seismic evaluation of existing buildings having non-seismic details, the reliability of this analysis method should be checked by the test results. The objective of this study is to verify the correlation between the experimental and analytical responses of a high-rise reinforced concrete frame-wall structure having non-seismic details by using DRAIN-2DX program[11] and the test results performed previously[1]. It is concluded that the behavior of the frame-wall model is mainly affected by the fixed-end rotation(uplift at base) and bending deformation of the wall and that the analysis with the LINKS model[10] in DRAIN-2DX describes them with good reliability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.7-12
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• 2008

In this study, the wide width effect that the increasing rate of drain current and the value of cutoff frequency decrease with larger finger number is observed. For modeling this effect, an improved SPICE MOSFET RF model that finger number-independent external source resistance is connected to a conventional BSIM3v3 RF model is developed. Better agreement between simulated and measured drain current and cutoff frequency at different finger number is obtained for the improved model than the conventional one, verifying the accuracy of the improved model for $0.13{\mu}m$ multi-finger MOSFET.

• Journal of the Korean Ceramic Society
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• v.38 no.10
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• pp.871-875
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• 2001

Cobalt silicidation at sidewall spacer edge of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with post annealing treatment for capacitor forming process has been investigated as a function of dopant species. Cobalt silicidation of nMOSFET with n-type Lightly Doped Drain (LDD) and pMOSFET with p-type LDD produces a well-developed cobalt silicide with its lateral growth underneath the sidewall spacer. In case of pMOSFET with n-type LDD, however, a void is formed at the sidewall spacer edge with no lateral growth of cobalt silicide. The void formation seems to be due to a retarded silicidation process at the LDD region during the first Rapid Thermal Annealing (RTA) for the reaction of Co with Si, resulting in cobalt mono silicide at the LDD region. The subsequent second RTA converts the cobalt monosilicide into cobalt disilicide with the consumption of Si atoms from the Si substrate, producing the void at the sidewall spacer edge in the Si region. The void formed at the sidewall spacer edge serves as a resistance in the current-voltage characteristics of the pMOSFET device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.43-47
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• 2013

In this work, we report extraction of the density-of-states (DOS) in polymer-based organic thin film transistors through the multi-frequency C-V spectroscopy. Extracted DOS is implemented into a TCAD simulator and obtained a consistent output curves with non-linear characteristics considering the contact resistance effect. We employed a Schottky contact model for the source and drain to fully reproduce a strong nonlinearity with proper physical mechanisms in the output characteristics even under a very small drain biases. For experimental verification of the model and extracted DOS, 2 different OTFTs (P3HT and PQT-12) are employed. By controlling the Schottky contact model parameters in the TCAD simulator, we accurately reproduced the nonlinearity in the output characteristics of OTFT.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1600-1603
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• 2009

In this work, we have fabricated inverted staggered ZnO TFTs with 1-${\mu}m$ resolution channel length by micro contact printing (${\mu}$-CP) method. Patterning of micro scale source/drain electrodes without etching is successfully achieved by micro contact printing method by using silver ink and polydimethylsiloxane (PDMS) stamp. And the time dependent characteristics of the sheet resistance show that Ag inklayer could be used as source and drain electrodes for ZnO TFTs.