• Journal of The Korean Society of Agricultural Engineers
• /
• v.52 no.3
• /
• pp.47-55
• /
• 2010

Investigations on the inundation damage and improvement measures were carried out centering around the protected horticultural complex concentrated in lowlands on the side of Geum river, in Nonsan and Buyeo, Chungnam. Most greenhouses were single-span plastic houses in this area, and tomato, strawberry and watermelon were cultivated mainly. 45.8 % of whole farmhouse were experienced in damage by inundation, and a frequency of the damage was average once in 11 years. The most urgent problem at the greenhouse culture in this area was showed in order of drainage improvement, irrigation water resources and energy saving. Consideration items in drainage improvement project for protected horticulture were showed in order of extending drain pumps, extending drain canals, using concrete flume in drain ditch. It needs to consider systematic plans that can restrain new establishment of greenhouses on the lowland paddy field in drainage area. It is difficult to remove greenhouses which are already established or prohibit cultivation. Therefore we should impose minimum duty items so that greenhouse tillers can cope with inundation. And it is thought that managing agency need to minimize farmers damage by improving drainage ability and introducing maintenance pattern that is different from rice cropping.

• Journal of Korean Society of Water and Wastewater
• /
• v.22 no.6
• /
• pp.681-687
• /
• 2008

It is well known that the water infiltration rate depends on soil properties such as soil water content, water head, capillary suction, density, hydraulic conductivity, and porosity. However, most of proposed infiltration models assume that the air phase is continuous and in equilibrium with the atmosphere or air compression and air entrapment on infiltration was not considered. This study presents experimental results on unsaturated water infiltration to relate air entrapment and hydraulic conductivity function based on soil air properties. The objectives of this study were to measure change of soil air pressure ahead of wetting front under air drain and air confined condition to find the confined air effect on infiltration rate, to reduce the entrapped air volume related with soil air pressure to increase the soil permeability, and to make a basis of infiltration process model for the purpose of improvement of infiltration rate in the homogeneous soil column. The results of the work show that soil air pressure increases according to increasement of the saturated soil depth rather than the wetting front depth during infiltration process.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.9
• /
• pp.1409-1418
• /
• 1990

Characteristics of NMOS transistors with phosphorus source/drain junctions formed by two-step rapid thermal diffusion (RTD) process using a solid diffusion source have been investigated. Phosphorus profiles after RTD were measured by SIMS analysis. In the case of 1100\ulcorner, 10sec RTD of, P, the specific contact resistance of n+ Si-Al was 2.4x10**-7 \ulcorner-cm\ulcorner which is 1/5 of the As junction The comparison fo P junction devices formed by RTD and conventional As junction devices shows that both short channel effect and hot carrier effect of P junction devices are smaller than those of As junction devices when the devices have same junction depths. P junction device had maximum of 0.4 times lower Isub/Id than As junction device. Characteristics of P junction formed by several different RTD conditions have been compared and 1000\ulcorner RTD sample had the smaller hot carrier generation. Also, it has been shown that the hot carrier generation can be futher reduced by forming the P junctions by 3-step RTD which has RTO-driven-in process additionally.

• Journal of the Korean Society for Precision Engineering
• /
• v.31 no.6
• /
• pp.497-504
• /
• 2014

The digital signage display is actively researched as the next generation of large FPD. To commercialize those digital signage display, the manufacturing cost must be downed with printing method instead of conventional photolithography. Here, we demonstrate a reverse offset printed TFT electrodes for the digital signage display. For the fabricated source/drain and gate electrode, we used Ag ink, silicone blanket, Clich$\acute{e}$ and reverse offset printer. We printed uniform TFT electrode patterns with narrow line width(10 ${\mu}m$ range) and thin thickness(nm range). In the end the printing source/drain and gate electrode are successfully achieved by optimization of experimental conditions such as Clich$\acute{e}$ surface treatment, ink coating process, delay time, off/set process and curing temperature. Also, we checked that the printing align accuracy was within 5 ${\mu}m$.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.5 no.3
• /
• pp.173-181
• /
• 2005

A new two dimensional (2-D) model for the potential distribution of fully depleted short-channel ion-implanted silicon MESFET's has been presented in this paper. The solution of the 2-D Poisson's equation has been considered as the superposition of the solutions of 1-D Poisson's equation in the lateral direction and the 2-D homogeneous Laplace equation with suitable boundary conditions. The minimum bottom potential at the interface of the depletion region due to the metal-semiconductor junction at the Schottky gate and depletion region due to the substrate-channel junction has been used to investigate the drain-induced barrier lowering (DIBL) and its effects on the threshold voltage of the device. Numerical results have been presented for the potential distribution and threshold voltage for different parameters such as the channel length, drain-source voltage, and implanted-dose and silicon film thickness.

• Journal of Satellite, Information and Communications
• /
• v.8 no.2
• /
• pp.36-43
• /
• 2013

In this study, the high current behaviors and double snapback mechanism of gate grounded_extended drain n-type MOSFET(GG_EDNMOS) device were analyzed in order to realize the robust electrostatic discharge(ESD) protection performances of high voltage operating display driver IC(DDIC) chips. Both the transmission line pulse(TLP) data and the thermal incorporated 2-dimensional simulation analysis as a function of ion implant conditions demonstrate a characteristic double snapback phenomenon after triggering of bipolar junction transistor(BJT) operation. Also, the background carrier density is proven to be a critical factor to affect the high current behavior of the GG_EDNMOS devices.

• Journal of the Korean Geotechnical Society
• /
• v.21 no.10
• /
• pp.41-48
• /
• 2005

The gravitational consolidation behavior of the dredged ground with horizontal drains is analyzed using a finite difference program developed for self-weight consolidation analysis with horizontal drains. The influence of area and direction of horizontal drains on the consolidation time and settlement is analyzed. Various field conditions such as the non-treated ground below horizontal drain installed ground, the accumulation of drained water at the end of horizontal drains, are also included in the analyses. It was found that a slight decrease of consolidation time is resulted in the twice increase of the sectional area of drains. Installing drains vertically can reduce the consolidation time more significantly than installing drains horizontally. The analyses showed quantitatively that the non-treated ground below the horizontal drain installed ground has much influence on long term consolidation settlement, and the accumulation of hydraulic head at the end of horizontal drains results in the increase of consolidation time and insufficient consolidation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.37 no.1
• /
• pp.48-55
• /
• 2024

The changes in threshold voltage and DIBL were investigated for changes in remanent polarization P_r and coercive field E_c, which determine the characteristics of the P-E hysteresis curve of ferroelectric in NCFET (negative capacitance FET). The threshold voltage and DIBL (drain-induced barrier lowering) were observed for a junctionless double gate MOSFET using a gate oxide structure of MFMIS (metal-ferroelectric-metal-insulator-semiconductor). To obtain the threshold voltage, series-type potential distribution and second derivative method were used. As a result, it can be seen that the threshold voltage increases when P_r decreases and E_c increases, and the threshold voltage is also maintained constant when the P_r/E_c is constant. However, as the drain voltage increases, the threshold voltage changes significantly according to P_r/E_c, so the DIBL greatly changes for P_r/E_c. In other words, when P_r/E_c=15 pF/cm, DIBL showed a negative value regardless of the channel length under the conditions of ferroelectric thickness of 10 nm and SiO₂ thickness of 1 nm. The DIBL value was in the negative or positive range for the channel length when the P_r/E_c is 25 pF/cm or more under the same conditions, so the condition of DIBL=0 could be obtained. As such, the optimal condition to reduce short channel effects can be obtained since the threshold voltage and DIBL can be adjusted according to the device dimension of NCFET and the P_r and E_c of ferroelectric.

• Journal of Korean Tunnelling and Underground Space Association
• /
• v.10 no.1
• /
• pp.37-47
• /
• 2008

Design and construction of tunnels require understanding the influence of groundwater. Particularly, it is essential to know how the drainage conditions at the tunnel boundary affect flow behavior of ground adjacent to the tunnels. In this study flow behavior of a leaking tunnel was investigated using physical model tests for tunnel depths and various hydraulic boundary conditions. Particular concerns were given to flow lines toward tunnels. Test results showed that the boundary conditions hardly influence on flow patterns and time required to reach steady state conditions. It is revealed that with an increase in water depth, flow lines concentrated to the drain holes. The physical tests were numerically simulated. Numerical results showed that the flow behavior was represented appropriately by considering filter-drain hole drainage rather than boundary drainage all over the lining.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.19 no.1
• /
• pp.1-6
• /
• 2006

High performance $Si_{0.8}Ge_{0.2}$ heterostructure metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated using well-controlled delta-doping of boron and $Si_{0.8}Ge_{0.2}$/Si heterostructure epitaxal layers grown by reduced pressure chemical vapor deposition. In this paper, we report 1/f noise characteristics of the SiGe pMOSFETs measured under various bias conditions of the gate and drain voltages changing in linear operation regions. From the noise spectral density, we found that the gate and drain voltage dependence of the noise represented same features, as usually scaled with $f^{-1}$ However, 1/f noise was found to be much lower in the device with boron delta-doped layer, by a factor of $10^{-1}_10^{-2}$ in comparison with the device fabricated without delta-doped layer. 1/f noise property of delta-doped device looks important because the device may replace bipolar transistors most commonly embedded in high-frequency oscillator circuits.