• Title/Summary/Keyword: drain bias change

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Dual Mode Power Amplifier for WiBro and Wireless LAN Using Drain Bias Switching (드레인 바이어스 스위칭을 이용한 와이브로/무선랜 이중 모우드 전력증폭기)

  • Lee, Young-Min;Koo, Kyung-Heon
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.3 s.357
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    • pp.1-6
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    • 2007
  • A drain bias switching technique is presented to enhance power added efficiency for WiBro and wireless LAN dual band and dual mode transmitter. Some simulations have been done to predict the effect of drain and gate bias change, and bias switching is proposed to get the higher efficiency for dual mode transmitter which generates different output power for different applications. With drain bias switching and simulated optimum fixed gate bias, the amplifier shows dramatic PAE improvement compared to the amplifier without bias switching. The drain and gate bias switching technique will be useful for multi mode communication system with various functions.

LNA Design Uses Active and Passive Biasing Circuit to Achieve Simultaneous Low Input VSWR and Low Noise (낮은 입력 정재파비와 잡음을 갖는 수동 및 능동 바이어스를 사용한 저잡음증폭기에 관한 연구)

  • Jeon, Joong-Sung
    • Journal of Advanced Marine Engineering and Technology
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    • v.32 no.8
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    • pp.1263-1268
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    • 2008
  • In this paper, the low noise power amplifier for GaAs FET ATF-10136 is designed and fabricated with active bias circuit and self bias circuit. To supply most suitable voltage and current, active bias circuit is designed. Active biasing offers the advantage that variations in the pinch-off voltage($V_p$) and saturated drain current($I_{DSS}$) will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets a gate-source voltage($V_{gs}$) for the desired drain voltage and drain current. Using resistive decoupling circuits, a signal at low frequency is dissipated by a resistor. This design method increases the stability of the LNA, suitable for input stage matching and gate source bias. The LNA is fabricated on FR-4 substrate with active and self bias circuit, and integrated in aluminum housing. As a results, the characteristics of the active and self bias circuit LNA implemented more than 13 dB and 14 dB in gain, lower than 1 dB and 1.1 dB in noise figure, 1.7 and 1.8 input VSWR at normalized frequency $1.4{\sim}1.6$, respectively.

Variable Bias Techniques for High Efficiency Power Amplifier Design (고효율 전력증폭기 설계를 위한 가변 바이어스 기법)

  • Lee, Young-Min;Kim, Kyung-Min;Koo, Kyung-Heon
    • Journal of Advanced Navigation Technology
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    • v.13 no.3
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    • pp.358-364
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    • 2009
  • This paper shows some variable bias techniques which can improve the power added efficiency(PAE) for the designed power amplifier. Some simulations have been done to get the effect of the bias change, and variable bias is adopted to get the higher efficiency for dual mode amplifier which generates two different output power levels. With drain bias change and a fixed gate bias, the amplifier shows PAE improvement compared to the fixed bias amplifier. In addition, this paper analyzed nonlinear distortion of the power amplifier and has used the digital predistortion which can result in 10dB ACPR improvement for the dual band amplifier.

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A study on the impedance effect of nonvolatile memory devices (비휘발성 기억소자의 저항효과에 관한 연구)

  • 강창수
    • Electrical & Electronic Materials
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    • v.8 no.5
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    • pp.626-632
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    • 1995
  • In this paper, The effect of the impedances in SNOSFET's memory devices has been developed. The effect of source and drain impedances measured by means of two bias resistances - field effect bias resistance by inner region, external bias resistance. The effect of the impedances by source and drain resistance shows the dependence of the function of voltages applied to the gate. It shows the differences of change in source drain voltage by means of low conductance state and high conductance state. It shows the delay of threshold voltages. The delay time of low conductance state and high conductance state by the impedances effect shows 3[.mu.sec] and 1[.mu.sec] respectively.

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Electron transport properties of Y-type zigzag branched carbon nanotubes

  • MaoSheng Ye;HangKong, OuYang;YiNi Lin;Quan Ynag;QingYang Xu;Tao Chen;LiNing Sun;Li Ma
    • Advances in nano research
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    • v.15 no.3
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    • pp.263-275
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    • 2023
  • The electron transport properties of Y-type zigzag branched carbon nanotubes (CNTs) are of great significance for micro and nano carbon-based electronic devices and their interconnection. Based on the semi-empirical method combining tight-binding density functional theory and non-equilibrium Green's function, the electron transport properties between the branches of Y-type zigzag branched CNT are studied. The results show that the drain-source current of semiconducting Y-type zigzag branched CNT (8, 0)-(4, 0)-(4, 0) is cut-off and not affected by the gate voltage in a bias voltage range [-0.5 V, 0.5 V]. The current presents a nonlinear change in a bias voltage range [-1.5 V, -0.5 V] and [0.5 V, 1.5 V]. The tangent slope of the current-voltage curve can be changed by the gate voltage to realize the regulation of the current. The regulation effect under negative bias voltage is more significant. For the larger diameter semiconducting Y-type zigzag branched CNT (10, 0)-(5, 0)-(5, 0), only the value of drain-source current increases due to the larger diameter. For metallic Y-type zigzag branched CNT (12, 0)-(6, 0)-(6, 0), the drain-source current presents a linear change in a bias voltage range [-1.5 V, 1.5 V] and is symmetrical about (0, 0). The slope of current-voltage line can be changed by the gate voltage to realize the regulation of the current. For three kinds of Y-type zigzag branched CNT with different diameters and different conductivity, the current-voltage curve trend changes from decline to rise when the branch of drain-source is exchanged. The current regulation effect of semiconducting Y-type zigzag branched CNT under negative bias voltage is also more significant.

Dependence of Electrical Characteristics on Back Bias in SOI Device (SOI(Silicon-on-Insulator) 소자에서 후면 Bias에 대한 전기적 특성의 의존성)

  • 강재경;박재홍;김철주
    • Proceedings of the Materials Research Society of Korea Conference
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    • 1993.05a
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    • pp.43-44
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    • 1993
  • In this study SOI MOSFET model of the structure with 4-terminals and 3-interfaces is proposed. An SOI MOSFET is modeled with the equivalent circuit considered the interface capacitances. Parameters of SOI MOSFET device are extracted, and the electrical characteristics due to back-bias change is simulated. In SOI-MOSFET model device we describe the characteristics of threshold voltage, subthreshold slope, maxium electrical field and drain currents in the front channel when the back channel condition move into accmulation, depletion, and inversion regions respectively.

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A Study on Design and Implementation of Low Noise Amplifier for Satellite Digital Audio Broadcasting Receiver (위성 DAB 수신을 위한 저잡음 증폭기의 설계 및 구현에 관한 연구)

  • Jeon, Joong-Sung;You, Jae-Hwan
    • Journal of Navigation and Port Research
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    • v.28 no.3
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    • pp.213-219
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    • 2004
  • In this paper, a LNA(Low Noise Amplifier) has been developed, which is operating at L-band i.e., 1452∼1492 MHz for satellite DAB(Digital Audio Brcadcasting) receiver. The LNA is designed to improve input and output reflection coefficient and VSWR(Voltage Standing Wave Ratio) by balanced amplifier. The LNA consists of low noise amplification stage and gain amplification stage, which make a using of GaAs FET ATF-10136 and VNA-25 respectively, and is fabricated by hybrid method. To supply most suitable voltage and current, active bias circuit is designed Active biasing offers the advantage that variations in $V_P$ and $I_{DSS}$ will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets $V_{gs}$ for the desired drain voltage and drain current. The LNA is fabricated on FR-4 substrate with RF circuit and bias circuit, and integrated in aluminum housing. As a reults, the characteristics of the LNA implemented more than 32 dB in gain. 0.2 dB in gain flatness. lower than 0.95 dB in noise figure, 1.28 and 1.43 each input and output VSWR, and -13 dBm in $P_{1dB}$.

Pulsed-Bias Pulsed-RF Passive Load-Pull Measurement of an X-Band GaN HEMT Bare-chip (X-대역 GaN HEMT Bare-Chip 펄스-전압 펄스-RF 수동 로드-풀 측정)

  • Shin, Suk-Woo;Kim, Hyoung-Jong;Choi, Gil-Wong;Choi, Jin-Joo;Lim, Byeong-Ok;Lee, Bok-Hyung
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.10 no.1
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    • pp.42-48
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    • 2011
  • In this paper, a passive load-pull using a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) bare-chip in X-band is presented. To obtain operation conditions that characteristic change by self-heating was minimized, pulsed drain bias voltage and pulsed-RF signal is employed. An accuracy impedance matching circuits considered parasitic components such as wire-bonding effect at the boundary of the drain is accomplished through the use of a electro-magnetic simulation and a circuit simulation. The microstrip line length-tunable matching circuit is employed to adjust the impedance. The measured maximum output power and drain efficiency of the pulsed load-pull are 42.46 dBm and 58.7%, respectively, across the 8.5-9.2 GHz band.

A Study of Suppression Current for LDMOS under Variation of Temperature (온도변화에 따른 LDMOS의 전류변동 억제에 관한 연구)

  • Jeon, Joong-Sung
    • Journal of Advanced Marine Engineering and Technology
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    • v.30 no.8
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    • pp.901-906
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    • 2006
  • In this paper, the power amplifier using active bias circuits for LDMOS(Lateral Diffused Metal Oxide Semiconductor) MRF-21180 is designed and fabricated. According to change the temperature, the gate voltage of LDMOS is controlled by the fabricated active bias circuits which is made of PNP transistor to suppress drain current. The driving amplifier using MRF-21125 and MRF-21060 is made to drive the LDMOS MRF-21180 power amplifier. The variation of current consumption in the fabricated 60 watt power amplifier has an excellent characteristics of less than 0.1 A, whereas a passive biasing circuit dissipates more than 0.5 A. The implemented power amplifier has the gain over 9 dB, the gain flatness of less than $\pm$0.1 dB and input and output return loss of less than -6 dB over the frequency range 2.11 $\sim$ 2.17 GHz. The DC operation point of this power amplifier at temperature variation 0 $^{\circ}C$ to 60 $^{\circ}C$ is fixed by active bias circuit.

The Study on Channel and Doping influence of MOSFET using TCAD (TCAD를 이용한 채널과 도핑 농도에 따른 MOSFET의 특성 분석)

  • 심성택;장광균;정정수;정학기;이종인
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2000.05a
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    • pp.470-473
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    • 2000
  • The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade in response to the constant demand for increased speed, decreased power, and increased patting density. The devices are scaled down day by day. Therefore, This paper investigates how MOSFET structures influence on transport properties in according to change of channel length and bias and, observes impact ionization between the drain and the gate. This paper proposes three models, i.e., conventional MOSFET, LDD MOSFET and EPI MOSFET. The gate lengths are 0.3$\mu\textrm{m}$ 0.15$\mu\textrm{m}$, 0.075$\mu\textrm{m}$ and scaling factor is λ = 2. We have presented MOSFET's characteristics such as I-V characteristic, impart ionization, electric field, using the TCAD. We have analyzed the adaptive channel and doping influences

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