• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.719-722
• /
• 2003

This work investigates the device degradation p-channel PD SOI devices at various applied voltages as well as stress temperatures with respect to Body-Contact SOI (BC-SOI) and Floating-Body SOI (FB-SOI) MOSFETs. It is observed that the drain current degradation at the gate voltage of the maximum gate current is more significant in FB-SOI devices than in BC-SOI devices. For a stress at the gate voltage of the maximum gate current and elevated temperature, it is worth noting that the $V_{PT}$ Will be decreased by the amount of the HEIP plus the temperature effects. For a stress at $V_{GS}$ = $V_{DS}$ . the drain current decreases moderately with stress time at room temperature but it decreases significantly at the elevated temperature due to the negative bias temperature instability.

• Journal of the Semiconductor & Display Technology
• /
• v.19 no.3
• /
• pp.82-87
• /
• 2020

The comprehensive and physics-based compact noise models for advanced CMOS devices were presented. The models incorporate important physical effects in nanoscale MOSFETs, such as the low frequency correlation effect between the drain and the gate, the trap-related phenomena, and QM (quantum mechanical) effects in the inversion layer. The drain current noise model was improved by including the tunneling assisted-thermally activated process, the realistic trap distribution, the parasitic resistance, and mobility degradation. The expression of correlation coefficient was analytically described, enabling the overall noise performance to be evaluated. With the consideration of QM effects, the comprehensive low frequency noise performance was simulated over the entire bias range.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.13 no.11
• /
• pp.895-900
• /
• 2000

In this paper, C-V characteristics based on the structure of GaAs MESFET’s has been proposed with wide range of applied voltages and temperatures. Small signal capacitance; gate-source and gate-drain capacitances are represented by analytical expressions which are classified into two different regions; linear and saturation regions with bias voltages. The expression contains two variables; the built-in voltage( $V_{vi}$ )and the depletion width(W). Submicron gate length MESFETs has been selected to prove the validity of the theoretical perdiction and shows good agreement with the experimental data over the wide range of applied voltages.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.6
• /
• pp.655-661
• /
• 2013

In this paper, the 1/f noise characteristics of n-channel MOSFET (NMOSFET) and p-channel MOSFET (PMOSFET) are analyzed in depth as a function of body bias. The normalized drain current noise, $S_{ID}/I_D{^2}$ showed strong dependence on the body bias in the sub-threshold region for both NMOSFET and PMOSFET, and NMOSFET showed stronger dependence than PMOSFET on the body bias. On the contrary, both of NMOSFET and PMOSFET do not exhibit the dependence of $S_{ID}/I_D{^2}$ on body bias in strong inversion region, although the noise mechanisms of two MOSFETs are different from each other.

• Proceedings of the IEEK Conference
• /
• 2004.06b
• /
• pp.347-350
• /
• 2004

The substrate parameters of Si MOSFET equivalent circuit model were directly extracted from measured S-Parameters in the GHz region by using simple 2-port parameter equations. Using the above extract ion method, bias and gate length dependent curves of substrate parameters in the RF region are obtained by varying drain voltage at several short channel devices with various gate lengths. These extract ion data will greatly contribute to scalable RF nonlinear substrate modeling.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2003.07a
• /
• pp.673-674
• /
• 2003

The reliability of TFT, crystallized by sequential lateral solidification (SLS) technology, has been studied High current damage is characterized by high gate bias (-20V) and drain bias (-10V). It is found that performance of SLS TFTs is enhanced by high current stress up to 300 sec of stress time for 20/8 (W/L) N-TFT. After that, TFT performance is degraded with the increase of the stress time. It is speculated from the experimental data that SLS TFTs initially contain a number of unstable defect states. Then, the defect states seem to be cured by high current stress.

• Journal of Information Display
• /
• v.13 no.1
• /
• pp.51-54
• /
• 2012

In this study, the bias-temperature stress and current-temperature stress induced by the electrical stabilities of half-Corbino hydrogenated-amorphous-silicon (a-Si:H) thin-film transistors (TFTs) with different gate electrode geometries fabricated on the same substrate were examined. The influence of the gate pattern on the threshold voltage shift of the half-Corbino a-Si:H TFTs is discussed in this paper. The results indicate that the half-Corbino a-Si:H TFT with a patterned gate electrode has enhanced power efficiency and improved aperture ratio when compared with the half-Corbino a-Si:H TFT with an unpatterned gate electrode and the same source/drain electrode geometry.

• Journal of the Semiconductor & Display Technology
• /
• v.14 no.2
• /
• pp.41-45
• /
• 2015

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.23 no.4
• /
• pp.1121-1133
• /
• 1998

In this paper, a new method is proposed for a simple andaccurate design of larage-sigal power amplifier using the output current- and volage- waveform analysis. An existing high-efficiency theory, Harmonic Loading, is modified to apply to a real device, and the notion of "actual bias point at large-signal input" is proposed. Based on the proposed theory, 2GHz band poweramplifier is implemented using HEMT device, and the implemented amplifier shows 14dBm output power, 46% drain efficienty, 38% power-added efficiency and 7.8dB gain at 2V bias voltage.

• Journal of Electrical Engineering and information Science
• /
• v.2 no.6
• /
• pp.208-211
• /
• 1997

We have fabricated a single-electron-tunneling(SET) transistor with a dual gate geometry based on the SOI structure prepared by SIMOX wafers. The split-gate is the lower-gate is the lower-level gate and located ∼ 100${\AA}$ right above the inversion layer 2DEG active channel, which yields strong carrier confinement with fully controllable tunneling potential barrier. The transistor is operating at low temperatures and exhibits the single electron tunneling behavior through nano-size quantum dot. The Coulomb-Blockade oscillation is demonstrated at 15mK and its periodicity of 16.4mV in the upper-gate voltage corresponds to the formation of quantum dots with a capacity of 9.7aF. For non-linear transport regime, Coulomb-staircases are clearly observed up to four current steps in the range of 100mV drain-source bias. The I-V characteristics near the zero-bias displays typical Coulomb-gap due to one-electron charging effect.