• Title/Summary/Keyword: doping concentration threshold voltage

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Effects of metal contacts and doping for high-performance field-effect transistor based on tungsten diselenide (WSe2)

  • Jo, Seo-Hyeon;Park, Jin-Hong
    • Proceedings of the Korean Vacuum Society Conference
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    • 2016.02a
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    • pp.294.1-294.1
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    • 2016
  • Transition metal dichalcogenides (TMDs) with two-dimensional layered structure, such as molybdenum disulfide (MoS2) and tungsten diselenide (WSe2), are considered attractive materials for future semiconductor devices due to its relatively superior electrical, optical, and mechanical properties. Their excellent scalability down to a monolayer based on the van der Waals layered structure without surface dangling bonds makes semiconductor devices based on TMD free from short channel effect. In comparison to the widely studied transistor based on MoS2, researchs focusing on WSe2 transistor are still limited. WSe2 is more resistant to oxidation in humid ambient condition and relatively air-stable than sulphides such as MoS2. These properties of WSe2 provide potential to fabricate high-performance filed-effect transistor if outstanding electronic characteristics can be achieved by suitable metal contacts and doping phenomenon. Here, we demonstrate the effect of two different metal contacts (titanium and platinum) in field-effect transistor based on WSe2, which regulate electronic characteristics of device by controlling the effective barreier height of the metal-semiconductor junction. Electronic properties of WSe2 transistor were systematically investigated through monitoring of threshold voltage shift, carrier concentration difference, on-current ratio, and field-effect mobility ratio with two different metal contacts. Additionally, performance of transistor based on WSe2 is further enhanced through reliable and controllable n-type doping method of WSe2 by triphenylphosphine (PPh3), which activates the doping phenomenon by thermal annealing process and adjust the doping level by controlling the doping concentration of PPh3. The doping level is controlled in the non-degenerate regime, where performance parameters of PPh3 doped WSe2 transistor can be optimized.

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Current Modeling for Accumulation Mode GaN Schottky Barrier MOSFET for Integrated UV Sensors

  • Park, Won-June;Hahm, Sung-Ho
    • Journal of Sensor Science and Technology
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    • v.26 no.2
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    • pp.79-84
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    • 2017
  • The drain current of the SB MOSFET was analytically modeled by an equation composed of thermionic emission and tunneling with consideration of the image force lowering. The depletion region electron concentration was used to model the channel electron concentration for the tunneling current. The Schottky barrier width is dependent on the channel electron concentration. The drain current is changed by the gate oxide thickness and Schottky barrier height, but it is hardly changed by the doping concentration. For a GaN SB MOSFET with ITO source and drain electrodes, the calculated threshold voltage was 3.5 V which was similar to the measured value of 3.75 V and the calculated drain current was 1.2 times higher than the measured.

Device Coupling Effects of Monolithic 3D Inverters

  • Yu, Yun Seop;Lim, Sung Kyu
    • Journal of information and communication convergence engineering
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    • v.14 no.1
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    • pp.40-44
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    • 2016
  • The device coupling between the stacked top/bottom field-effect transistors (FETs) in two types of monolithic 3D inverter (M3INV) with/without a metal layer in the bottom tier is investigated, and then the regime of the thickness TILD and dielectric constant εr of the inter-layer distance (ILD), the doping concentration Nd (Na), and length Lg of the channel, and the side-wall length LSW where the stacked FETs are coupled are studied. When Nd (Na) < 1016 cm-3 and LSW < 20 nm, the threshold voltage shift of the top FET varies almost constantly by the gate voltage of the bottom FET, but when Nd (Na) > 1016 cm-3 or LSW > 20 nm, the shift decreases and increases, respectively. M3INVs with TILD ≥ 50 nm and εr ≤ 3.9 can neglect the interaction between the stacked FETs, but when TILD or εr do not meet the above conditions, the interaction must be taken into consideration.

Analysis of Threshold Voltage Characteristics for Double Gate MOSFET Based on Scaling Theory (스켈링이론에 따른 DGMOSFET의 문턱전압 특성분석)

  • Jung, Hak-Kee;Han, Ji-Hyung;Jeong, Dong-Soo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.05a
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    • pp.683-685
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    • 2012
  • This paper have presented the analysis of the change for threshold voltage and drain induced barrier lowering among short channel effects occurred in subthreshold region for double gate(DG) MOSFET with two gates to be next-generation devices, based on scaling theory. To obtain the analytical solution of Poisson's equation, Gaussian function been used as carrier distribution to analyze closely for experimental results, and the threshold characteristics have been analyzed for device parameters such as channel thickness and doping concentration and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold chatacteristics. As a result to apply scaling theory, we know the threshold voltage and drain induced barrier lowering is changed, and the deviation rate is changed for device parameters for DGMOSFET.

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Analysis of Transport Characteristics for Double Gate MOSFET using Analytical Current-Voltage Model (해석학적 전류-전압모델을 이용한 이중게이트 MOSFET의 전송특성분석)

  • Jung Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.9
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    • pp.1648-1653
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    • 2006
  • In this paper, transport characteristics have been investigated using analytical current-voltage model for double gate MOSFET(DGMOSFET). Scaling down to 100nm of gate length for MOSFET can bring about various problems such as a threshold voltage roll-off and increasing off current by tunneling since thickness of oxide is down by 1.fnm and doping concentration is increased. A current-voltage characteristics have been calculated according to changing of channel length,using analytical current-voltage relation. The analytical model has been verified by calculating I-V relation according to changing of oxide thickness and channel thickness as well as channel length. A current-voltage characteristics also have been compared and analyzed for operating temperature. When gate voltage is 2V, it is shown that a current-voltage characteristic in 77K is superior to in room temperature.

CVD로 성장된 다결정 3C-SiC 박막의 전기적 특성

  • An, Jeong-Hak;Jeong, Gwi-Sang
    • Proceedings of the Korean Society Of Semiconductor Equipment Technology
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    • 2007.06a
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    • pp.179-182
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    • 2007
  • Polycrystaline (poly) 3C-SiC thin film on n-type and p-type Si were deposited by APCVD using HMDS, $H_2$, and Ar gas at $1180^{\circ}C$ for 3 hour. And then the schottky diode with Au/poly 3C-Sic/Si(n-type) structure was fabricated. Its threshold voltage ($V_d$), breakdown voltage, thickness of depletion layer, and doping concentration ($N_D$) value were measured as 0.84 V, over 140 V, 61nm, and $2.7{\times}10^{19}\;cm^3$, respectively. The p-n junction diode fabricated by poly 3C-SiC was obtained like characteristics of single 3C-SiC p-n junction diode. Therefore, its poly 3C-SiC thin films are suitable MEMS applications in conjuction with Si fabrication technology.

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Negative Differential Resistance Devices with Ultra-High Peak-to-Valley Current Ratio and Its Multiple Switching Characteristics

  • Shin, Sunhae;Kang, In Man;Kim, Kyung Rok
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.6
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    • pp.546-550
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    • 2013
  • We propose a novel negative differential resistance (NDR) device with ultra-high peak-to-valley current ratio (PVCR) by combining pn junction diode with depletion mode nanowire (NW) transistor, which suppress the valley current with transistor off-leakage level. Band-to-band tunneling (BTBT) Esaki diode with degenerately doped pn junction can provide multiple switching behavior having multi-peak and valley currents. These multiple NDR characteristics can be controlled by doping concentration of tunnel diode and threshold voltage of NW transistor. By designing our NDR device, PVCR can be over $10^4$ at low operation voltage of 0.5 V in a single peak and valley current.

Random Dopant Fluctuation Effects of Tunneling Field-Effect Transistors (TFETs) (터널링 전계효과 트랜지스터의 불순물 분포 변동 효과)

  • Jang, Jung-Shik;Lee, Hyun Kook;Choi, Woo Young
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.12
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    • pp.179-183
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    • 2012
  • The random dopant fluctuation (RDF) effects of tunneling field-effect transistors (TFETs) have been observed by using atomistic 3-D device simulation. Due to extremely low body doping concentration, the RDF effects of TFETs have not been seriously investigated. However, in this paper, it has been found that the randomly generated and distributed source dopants increase the variation of threshold voltage ($V_{th}$), drain induced current enhancement (DICE) and subthreshold slope (SS) of TFETs. Also, some ways of relieving the RDF effects of TFETs have been presented.

A Study on High Voltage SiC-IGBT Device Miniaturization (고내압 SiC-IGBT 소자 소형화에 관한 연구)

  • Kim, Sung-Su;Koo, Sang-Mo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.26 no.11
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    • pp.785-789
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    • 2013
  • Silicon Carbide (SiC) is the material with the wide band-gap (3.26 eV), high critical electric field (~2.3 MV/cm), and high bulk electron mobility (~900 $cm^2/Vs$). These electronic properties allow attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. In general, device design has a significant effect on the switching and electrical characteristics. It is known that in this paper, we demonstrated that the switching performance and breakdown voltage of IGBT is dependent with doping concentration of p-base region and drift layer by using 2-D simulations. As a result, electrical characteristics of SiC-IGBT deivce is higher breakdown voltage ($V_B$= 1,600 V), lower on-resistance ($R_{on}$= 0.43 $m{\Omega}{\cdot}cm^2$) than Si-IGBT. Also, we determined that processing time and cost is reduced by the depth of n-drift region of IGBT was reduced.

Dependence of Drain Induced Barrier Lowering for Ratio of Channel Length vs. Thickness of Asymmetric Double Gate MOSFET (비대칭 DGMOSFET에서 채널길이와 두께 비에 따른 DIBL 의존성 분석)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.6
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    • pp.1399-1404
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    • 2015
  • This paper analyzed the phenomenon of drain induced barrier lowering(DIBL) for the ratio of channel length vs. thickness of asymmetric double gate(DG) MOSFET. DIBL, the important secondary effect, is occurred for short channel MOSFET in which drain voltage influences on potential barrier height of source, and significantly affects on transistor characteristics such as threshold voltage movement. The series potential distribution is derived from Poisson's equation to analyze DIBL, and threshold voltage is defined by top gate voltage of asymmetric DGMOSFET in case the off current is 10-7 A/m. Since asymmetric DGMOSFET has the advantage that channel length and channel thickness can significantly minimize, and short channel effects reduce, DIBL is investigated for the ratio of channel length vs. thickness in this study. As a results, DIBL is greatly influenced by the ratio of channel length vs. thickness. We also know DIBL is greatly changed for bottom gate voltage, top/bottom gate oxide thickness and channel doping concentration.