• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.4
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• pp.809-815
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• 2000

The box capacitor structure with HSG-Si described here reliably achieves a cell capacitance of 28fF with a cell area of a $0.4820\mum^2$ for 128Mbit DRAM. An HSG-Si formation technology with seeding method, which employs Si2H6 molecule irradiation and annealing, was applied for realizing 64Mbit and larger DRAMS. By using this technique, grain size controlled HSG-Si can be fabricated on in-situ phosphorous doped amorphous silicon electrodes. The HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors.The box capacitor structure with HSG-Si described here reliably achieves a cell capacitance of 28fF with a cell area of a $0.4820\mum^2$ for 128Mbit DRAM. An HSG-Si formation technology with seeding method, which employs Si2H6 molecule irradiation and annealing, was applied for realizing 64Mbit and larger DRAMS. By using this technique, grain size controlled HSG-Si can be fabricated on in-situ phosphorous doped amorphous silicon electrodes. The HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors.

• Korean Journal of Materials Research
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• v.24 no.7
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• pp.375-380
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• 2014

Solar cells exhibit different power outputs in different climates. In this study, the temperature dependence of open-circuit voltage(V-oc), short-circuit current(I-sc), fill factor(FF) and the efficiency of screen-printed single-crystal silicon solar cells were studied. One group was fabricated with homogeneously-doped emitters and another group was fabricated with selectively-doped emitters. While varying the temperature (25, 40, 60 and $80^{\circ}C$), the current-voltage characteristics of the cells were measured and the leakage currents extracted from the current-voltage curve. As the temperature increased, both the homogeneously-doped and selectively-doped emitters showed a slight increase in I-sc and a rapid degradation of V-oc. The FF and efficiency also decreased as temperature increased in both groups. The temperature coefficient for each factor was calculated. From the current-voltage curve, we found that the main cause of V-oc degradation was an increase in the intrinsic carrier concentration. The temperature coefficients of the two groups were compared, leading to the idea that structural effects could also affect the temperature dependence of current-voltage characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.02a
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• pp.284.2-284.2
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• 2009

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1261-1263
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• 1997

Two kinds of optically-triggered p-i-n switches with planar and V-groove structures have been fabricated with gold-doped silicon. The V-groove device exhibits a higher threshold voltage and is more sensitive to light. The minimum optical power indicates that a certain minimum illumination is required to optically turn on the silicon p-i-n devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.112-117
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• 2008

Vertical interconnection scheme using novel silicon-through-via for 3D MEMS devices or stacked package is proposed and fabricated to demonstrate its feasibility. The suggested silicon-through-via replaces electroplated copper, which is used as an interconnecting material in conventional through-via, with doped silicon. Adoption of doped silicon instead of metal eliminates thermal-mismatch-induced stress, which can make troubles in high temperature MEMS processes, such as wafer bonding and LP-CVD(low pressure chemical vapor deposition). Two silicon layers of $30{\mu}m$ thickness are stacked on the substrate. The through-via arrays with spacing $40{\mu}m$ and $50{\mu}m$ are fabricated successfully. Electrical characteristics of the through-via are measured and analyzed. The measured resistance of the silicon-through-via is $169.9\Omega$.

• Biotechnology and Bioprocess Engineering:BBE
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• v.8 no.4
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• pp.252-256
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• 2003

In this paper we describe the status of a silicon-based microelectrode for neural recording and an advanced neural interface. We have developed a silicon neural probe, using a combination of plasma and wet etching techniques. This process enables the probe thickness to be controlled precisely. To enhance the CMOS compatibility in the fabrication process, we investigated the feasibility of the site material of the doped polycrystalline silicon with small grains of around 50 nm in size. This silicon electrode demonstrated a favorable performance with respect to impedance spectra, surface topography and acute neural recording. These results showed that the silicon neural probe can be used as an advanced microelectrode for neurological applications.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.346.2-346.2
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• 2016

The rear side contact recombination in the crystalline silicon solar cell could be reduced by back surface field. We formed polycrystalline silicon as a back surface field through crystallization of amorphous silicon. A thin silicon oxide applied to the passivation layer. We used quasi-steady-state photoconductance measurement to analyze electrical properties with various annealing condition. And, blister formed on surface of wafer during the annealing process. We observed the blister after varied annealing process with wafer of various surface. Shape and density of blister is influenced by various annealing temperature and process time. As the annealing temperature became higher, the average diameter of blister is decreased and total number of blister is increased. The sample with the $600^{\circ}C$ annealing temperature and 1 min annealing time exhibited the highest implied open circuit voltage and lifetime. We predicted that the various shape and density of blister affects the lifetime and implied open circuit voltage.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.1
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• pp.7-19
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• 1981

Anodization method is utilized in order to measure diffusion profiles of boron and arsenic in silicon. The solution used for silicon anodization is Ethylene glycol +KNO3(0.04N), The thickness of silicon which is consumed by a single 200V anodization is 460$\pm$40A regardless of wafer type. The profiles of boron and arsenic in silicon after predeposition process are investigated. The diffusion coefficients of both dopants depending on impurity concentration are extrated from these profiles. The base pull-in effect has been observed in prototype npn transistors with arsenic doped emitter.

• Journal of Integrative Natural Science
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• v.7 no.4
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• pp.221-226
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• 2014

Optically encoded porous silicon smart particles were successfully fabricated from the free-standing porous silicon thin films using ultrasono-method. DBR PSi was prepared by an electrochemical etch of heavily doped $p^{{+}{+}}$-type silicon wafer. DBR PSi was prepared by using a periodic pseudo-square wave current. The surface-modified DBR PSi was prepared by either thermal oxidation or thermal hydrosilylation. Free-standing DBR PSi films were generated by lift-off from the silicon wafer substrate using an electropolishing current. Free-standing DBR PSi films were ultrasonicated to create DBR-structured porous smart particles. Optical characteristics of porous smart particles were measured by FT-IR spectroscopy. The surface morphology of porous smart particles was determined by FE-SEM.

• Journal of the Korean Vacuum Society
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• v.17 no.1
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• pp.46-50
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• 2008

Optical images on the porous silicon exhibiting Febry-Perot fringe pattern have been prepared by using an electrochemical etching of p-type silicon wafer (boron-doped,<100> orientation, resistivity $0.8{\sim}1.2m{\Omega}-cm$) and beam projector. The images remained in the substrate displayed an optical images correlating to the optical pattern and could be useful for optical data storage. A decrease in the effective optical thickness of the Febry-Perot layers was observed, indicative of a change in refractive index induced by exposing of porous silicon to the white light. This provides the ability to fabricate complex optical encoding in the surface of silicon.