• Journal of the Korean Crystal Growth and Crystal Technology
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• v.23 no.5
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• pp.213-217
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• 2013

The GaN layer was typical III-V nitride semiconductor and was grown on the sapphire substrate which cheap and convenient. However, sapphire substrate is non-conductivity, low thermal conductivity and has large lattice mismatch with the GaN layer. In this paper, the poly GaN epilayer was grown by HVPE on the metallic compound graphite substrate with good heat dissipation, high thermal and electrical conductivity. We tried to observe the growth mechanism of the GaN epilayer grown on the amorphous metallic compound graphite substrate. The HCl and $NH_3$ gas were flowed to grow the GaN epilayer. The temperature of source zone and growth zone in the HVPE system was set at $850^{\circ}C$ and $1090^{\circ}C$, respectively. The GaN epilayer grown on the metallic compound graphite substrate was observed by SEM, EDS, XRD measurement.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.27-37
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• 1999

A CMOS ReadOut Integrated Circuit (ROlC) for InfraRed Focal Plane Array (IRFPA) detector is presented, which is a key component in uncooled thermal imaging systems. The ROIC reads out signals from $64\times64$ Barium Strontium Titanate (BST) infrared detector array, then outputs pixel signals sequentially after amplifying and noise filtering. Various design requirements and constraints have been considered including impedance matching, low noise, low power dissipation and small detector pitch. For impedance matching between detector and pre~amplifier, a new circuit based on MOS diode structure is devised, which can be easily implemented using standard CMOS process. Also, tunable low pass filter with single~pole is used to suppress high frequency noise. In additions, a clamping circuit is adopted to enhance the signal~to-noise ratio of the readout output signals. The $64\times64$ IRFPA ROIC is designed using $0.65-\mu\textrm{m}$ 2P3M (double poly, tripple metal) N~Well CMOS process. The core part of the chip contains 62,000 devices including transistors, capacitors and resistors on an area of about $6.3-mm\times6.7-mm$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.1-9
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• 2006

In this paper, a couple of 10Gb/s transimpedance amplifiers are realized in a 0.18um standard CMOS technology for optical communication applications. First, the voltage-mode inverter TIA(I-TIA) exploits inverter input configuration to achieve larger effective gm, thus reducing the input impedance and increasing the bandwidth. I-TIA demonstrates $56dB{\Omega}$ transimpedance gain, 14GHz bandwidth for 0.25pF photodiode capacitance, and -16.5dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. However, both its inherent parasitic capacitance and the package parasitics deteriorate the bandwidth significantly, thus mandating very judicious circuit design. Meanwhile, the current-mode RGC TIA incorporates the regulated cascade input configuration, and thus isolates the large input parasitic capacitance from the bandwidth determination more effectively than the voltage-mode TIA. Also, the parasitic components give much less impact on its bandwidth. RGC TIA provides $60dB{\Omega}$ transimpedance gain, 10GHz bandwidth for 0.25pF photodiode capacitance, and -15.7dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. Main drawback is the power dissipation which is 4.5 times larger than the I-TIA.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.1
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• pp.135-139
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• 2015

The address discharge time lags are investigated in each subfield time in AC plasma display panel and a modified driving waveform is proposed to reduce the address discharge time lag by applying different additional scan voltage under no misfiring discharge production. The weak plasma discharge in AC PDP is generated by applying high positive-going ramp waveform to the scan electrode during the first reset period and that induce the production of the priming particle and wall charge. Because the wall charge becomes the wall voltage in a cell, the wall plus external address voltage produce the address discharge. However, as the wall charge in a cell is gradually disappeared as time passed, the address discharge time in the subfield time for 1 TV frame is lagged. In the first subfield time, the address discharge is faster produced than the other subfield time because the wall charge are much remained by the high positive-going ramp voltage during the reset period in the first subfield time. Meanwhile, from the second to last subfield, the address discharge production time is gradually delayed due to the dissipation of the wall charge in a cell. In this study, the address discharge time lags are measured in each subfield time and the total address discharge time lags are shortened by applying the different additional scan voltage during the address period in each the subfield time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.36-44
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• 2007

This paper presented a hybrid ternary encoding scheme using 3-valued logic. It can adapt to the delay-insensitive(DI) model. We designed an asynchronous wrapper for the hybrid ternary encoding scheme to communicate with various asynchronous encoding schemes. It reduced about 50% of transmission lines and power consumption compared with the conventional 1-of-4 and ternary encoding scheme. The proposed wrappers were designed and simulated using the $0.18-{\mu}m$ standard CMOS technology. As a result, the asynchronous wrapper operated over 2 GHz communicating with a system bus. Moreover, the power dissipation of the system bus adapted the hybrid ternary encoding logic decreases 65%, 43%, and 36% of the dual-rail, 1-of-4, and ternary encoding scheme, respectively. The proposed data encoding scheme and the wrapper circuit can be useful for asynchronous high-speed and low-power asynchronous interface.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.137-147
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• 2013

In this paper, an 1.2V 8b 1GS/s A/D Converter(ADC) based on a folding architecture with a resistive interpolation technique is described. In order to overcome the asymmetrical boundary-condition error of conventional folding ADCs, a novel scheme with an odd number of folding blocks and a fractional folding rate are proposed. Further, a new digital encoding technique with an arithmetic adder is described to implement the proposed fractional folding technique. The proposed ADC employs an iterating offset self-calibration technique and a digital error correction circuit to minimize device mismatch and external noise The chip has been fabricated with a 1.2V 0.13um 1-poly 6-metal CMOS technology. The effective chip area is $2.1mm^2$ (ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$) and the power dissipation is about 350mW including calibration engine at 1.2V power supply. The measured result of SNDR is 46.22dB, when Fin = 10MHz at Fs = 1GHz. Both the INL and DNL are within 1LSB with the self-calibration circuit.

• Bulletin of the Korean Chemical Society
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• v.35 no.3
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• pp.758-764
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• 2014

Femtosecond vibrational spectroscopy was used to measure the vibrational population relaxation time ($T_1$) of different anions bound to ferric myoglobin ($Mb^{III}$) and hemoglobin ($Hb_{III}$) in $D_2O$ at 293 K. The $T_1$ values of the anti-symmetric stretching (${\nu}_1$) mode of NCS in the $NCS^-$ bound to $Mb^{III}$ ($Mb^{III}$NCS) and $Hb_{III}$ ($Hb_{III}$NCS) in $D_2O$ are $7.2{\pm}0.2$ and $6.6{\pm}0.2$ ps, respectively, which are smaller than that of free NCS. in $D_2O$ (18.3 ps). The $T_1$ values of the ${\nu}_1$ mode of NCO in the $NCO^-$ bound to $Mb^{III}$ ($Mb^{III}$NCO) and $Hb_{III}$ ($Hb_{III}$NCO) in $D_2O$ are $2.4{\pm}0.2$ and $2.6{\pm}0.2$ ps, respectively, which are larger than that of free $NCO^-$ in $D_2O$ ($1.9{\pm}0.2$ ps). The smaller $T_1$ values of the ${\nu}_1$ mode of the heme-bound NCS suggest that intramolecular vibrational relaxation (VR) is the dominant relaxation pathway for the excess vibrational energy. On the other hand, the longer $T_1$ values of the ${\nu}_1$ mode of the heme-bound NCO suggest that intermolecular VR is the dominant relaxation pathway for the excess vibrational energy in the ${\nu}_1$ mode of $NCO^-$ in $D_2O$, and that intramolecular VR becomes more important in the vibrational energy dissipation of the ${\nu}_1$ mode of NCO in $Mb^{III}$NCO and $Hb_{III}$NCO.

• Journal of Korean Society of Steel Construction
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• v.23 no.3
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• pp.337-347
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• 2011

In this study, seismic resistance of concrete encased U-shaped steel beam-to-steel H-shaped column connections was evaluated. Three specimens of the beam-to-column connection were tested under cyclic loading. The composite beam was integrated with concrete slab using studs. Re-bars for negative moment were placed in the slab. The primary test parameter was the details of the connections, which are strengthening and weakening strategies for the beam end and the degree of composite action. The depth of the composite beams was 600mm including the slab thickness. The steel beam and the re-bars in the slab were weld-connected to the steel column. For the strengthening strategy, cover plates were weld-connected to the bottom and top flanges of the steel beam. For the weakening strategy, a void using styrofoam box was located inside the core concrete at the potential plastic hinge zone. The test results showed that the fully composite specimens exhibited good strength, deformation, and energy dissipation capacities. The deformation capacity of the beam exceeded 4% rotation angle, which is the requirement for the Special Moment Frame.

• Journal of Korean Society of Steel Construction
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• v.28 no.6
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• pp.439-448
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• 2016

Extended end-plate connections(EEPC) are a type of connection applied in Pre-Engineered Building structures comprising beam-column connections of steel structures or tapered members. Extended end-plate connections(EEPC) show different behavioral characteristics owing to the influence of plate thickness, gauge distance of high strength bolt, diameter of high strength bolt frame, and the number of high strength bolts. In the USA and Europe, extended end-plate connections(EEPC) are applied in beam-column connections of steel structures in various forms; however, these are not widely applied in structures in Korea.This can be attributed to the fact that the proposal of design strength types for extended end-plate connections(EEPC), proposal of connection specifications, evaluation of seismic performance, and are not being performed appropriately. Therefore, the purpose of this study is to provide basic data for the domestic application of Unstiffened extended endplate connections. To realize this, nonlinear finite element analysis was conducted on a 12-mm thick Unstiffened extended endplate connections.

• Journal of Korean Society of Steel Construction
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• v.28 no.6
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• pp.467-476
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• 2016

For the connections between modular units in modular buildings, the bolted joints with connector plates are used commonly. The strength of structure is determined by the weakest part of structure and the connections may be weaker than the members being joined. Therefore, to check the safety of modular building, the structural performance of connections between modular units as well as that of beam-to-column connections should be evaluated. In this study, the behavior of module to module connection with straight and cross shaped connector plates is investigated by lateral cyclic tests according to KBC2009 0722.2.4 which shall be conducted by controlling the story drift angle in the width and the longitudinal direction respectively. All of test results generally show the stable ductile behavior up to 0.04rad drift levels and the tests in longitudinal direction show a superior energy dissipation per cycle in each of the load steps. However, the straight shaped connector plates have the degradation of stiffness with cyclic loading and the larger drift angle of column than the cross shaped connector plates.