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Design of Asynchronous System Bus Wrappers based on a Hybrid Ternary Data Encoding Scheme  

Lim, Young-Il (Dept. of Computer and Communication Engineering and Research Institute for Computer and Information Communication, Chungbuk National University)
Lee, Je-Hoon (CBNU BK21 Chungbuk Information Technology Center, Chungbuk National University)
Lee, Seung-Sook (Dept. of Computer and Communication Engineering and Research Institute for Computer and Information Communication, Chungbuk National University)
Cho, Kyoung-Rok (Dept. of Computer and Communication Engineering and Research Institute for Computer and Information Communication, Chungbuk National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.44, no.1, 2007 , pp. 36-44 More about this Journal
Abstract
This paper presented a hybrid ternary encoding scheme using 3-valued logic. It can adapt to the delay-insensitive(DI) model. We designed an asynchronous wrapper for the hybrid ternary encoding scheme to communicate with various asynchronous encoding schemes. It reduced about 50% of transmission lines and power consumption compared with the conventional 1-of-4 and ternary encoding scheme. The proposed wrappers were designed and simulated using the $0.18-{\mu}m$ standard CMOS technology. As a result, the asynchronous wrapper operated over 2 GHz communicating with a system bus. Moreover, the power dissipation of the system bus adapted the hybrid ternary encoding logic decreases 65%, 43%, and 36% of the dual-rail, 1-of-4, and ternary encoding scheme, respectively. The proposed data encoding scheme and the wrapper circuit can be useful for asynchronous high-speed and low-power asynchronous interface.
Keywords
asynchronous circuit; wrapper; data encoding; delay-insensitive; hybird ternary;
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