Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of Asynchronous System Bus Wrappers based on a Hybrid Ternary Data Encoding Scheme

하이브리드 터너리 데이터 인코딩 기반의 비동기식 시스템 버스 래퍼 설계

  • Lim, Young-Il (Dept. of Computer and Communication Engineering and Research Institute for Computer and Information Communication, Chungbuk National University) ;
  • Lee, Je-Hoon (CBNU BK21 Chungbuk Information Technology Center, Chungbuk National University) ;
  • Lee, Seung-Sook (Dept. of Computer and Communication Engineering and Research Institute for Computer and Information Communication, Chungbuk National University) ;
  • Cho, Kyoung-Rok (Dept. of Computer and Communication Engineering and Research Institute for Computer and Information Communication, Chungbuk National University)
  • 임영일 (충북대학교 정보통신공학과 컴퓨터정보통신연구소) ;
  • 이제훈 (충북대학교 BK21) ;
  • 이승숙 (충북대학교 정보통신공학과 컴퓨터정보통신연구소) ;
  • 조경록 (충북대학교 정보통신공학과 컴퓨터정보통신연구소)
  • Published : 2007.01.25
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Abstract

This paper presented a hybrid ternary encoding scheme using 3-valued logic. It can adapt to the delay-insensitive(DI) model. We designed an asynchronous wrapper for the hybrid ternary encoding scheme to communicate with various asynchronous encoding schemes. It reduced about 50% of transmission lines and power consumption compared with the conventional 1-of-4 and ternary encoding scheme. The proposed wrappers were designed and simulated using the $0.18-{\mu}m$ standard CMOS technology. As a result, the asynchronous wrapper operated over 2 GHz communicating with a system bus. Moreover, the power dissipation of the system bus adapted the hybrid ternary encoding logic decreases 65%, 43%, and 36% of the dual-rail, 1-of-4, and ternary encoding scheme, respectively. The proposed data encoding scheme and the wrapper circuit can be useful for asynchronous high-speed and low-power asynchronous interface.

본 논문은 Delay-Insensitive(DI) 지연 모델을 갖는 비동기식 회로에 3치 전압 레벨을 사용한 하이브리드 터너리 데이터 전송 방식을 제안하고, 이를 이용하여 다양한 비동기 프로토콜과의 데이터 송신 및 수신을 위한 래퍼를 설계하였다. 제안된 하이브리드 터너리 데이터 전송 방식은 기존의 2 선식 전송 방식이나 1-of-4 전송 방식에 비해 데이터 전송선을 50% 줄일 수 있으며, 터너리 전송 방식과 비교하였을 때도 50%의 신호 천이 감소 결과를 보였다. 본 논문에서는 $0.18-{\mu}m$ CMOS 공정을 적용하여 래퍼를 설계하고 검증하였다. 하이브리드 터너리 전송 방식이 적용된 래퍼는 2 GHz 이상의 속도로 동작 하였으며 2 선식, 1-of-4, 그리고 터너리 전송 방식에 비해 각각 65%, 43%, 36%의 소비 전력이 줄어든 결과를 보였다. 제안된 전송 방식과 설계된 래퍼 회로는 비동기식 고속 및 저전력 인터페이스로 사용 가능하다.

Keywords

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